Module: Mesa Branch: main Commit: 778000ec7f5b57743dec1cf1d1480875126b90bd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=778000ec7f5b57743dec1cf1d1480875126b90bd
Author: Eric Engestrom <e...@igalia.com> Date: Sun Dec 3 19:41:49 2023 +0000 radv: update symbols that have become aliases for newer ones All of these have been renamed in the spec (usually by being promoted); renamed them in our code too. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26490> --- src/amd/vulkan/layers/radv_rra_layer.c | 2 +- src/amd/vulkan/layers/radv_sqtt_layer.c | 8 ++++---- src/amd/vulkan/radv_cmd_buffer.c | 4 ++-- src/amd/vulkan/radv_descriptor_set.c | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/layers/radv_rra_layer.c b/src/amd/vulkan/layers/radv_rra_layer.c index 2c1e83526a6..7a1c42083f2 100644 --- a/src/amd/vulkan/layers/radv_rra_layer.c +++ b/src/amd/vulkan/layers/radv_rra_layer.c @@ -166,7 +166,7 @@ handle_accel_struct_write(VkCommandBuffer commandBuffer, struct vk_acceleration_ .sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2, .srcStageMask = VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, .srcAccessMask = VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR, - .dstStageMask = VK_PIPELINE_STAGE_2_TRANSFER_BIT, + .dstStageMask = VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT, .dstAccessMask = VK_ACCESS_2_TRANSFER_READ_BIT, }; diff --git a/src/amd/vulkan/layers/radv_sqtt_layer.c b/src/amd/vulkan/layers/radv_sqtt_layer.c index 1ec1383eb2f..2707b32d785 100644 --- a/src/amd/vulkan/layers/radv_sqtt_layer.c +++ b/src/amd/vulkan/layers/radv_sqtt_layer.c @@ -741,7 +741,7 @@ radv_sqtt_wsi_submit(VkQueue _queue, uint32_t submitCount, const VkSubmitInfo2 * radv_describe_queue_present(queue, cpu_timestamp, gpu_timestamp_ptr); - result = queue->device->layer_dispatch.rgp.QueueSubmit2KHR(_queue, 1, &sqtt_submit, _fence); + result = queue->device->layer_dispatch.rgp.QueueSubmit2(_queue, 1, &sqtt_submit, _fence); if (result != VK_SUCCESS) goto fail; @@ -756,7 +756,7 @@ fail: } VKAPI_ATTR VkResult VKAPI_CALL -sqtt_QueueSubmit2KHR(VkQueue _queue, uint32_t submitCount, const VkSubmitInfo2 *pSubmits, VkFence _fence) +sqtt_QueueSubmit2(VkQueue _queue, uint32_t submitCount, const VkSubmitInfo2 *pSubmits, VkFence _fence) { RADV_FROM_HANDLE(radv_queue, queue, _queue); const bool is_gfx_or_ace = queue->state.qf == RADV_QUEUE_GENERAL || queue->state.qf == RADV_QUEUE_COMPUTE; @@ -766,7 +766,7 @@ sqtt_QueueSubmit2KHR(VkQueue _queue, uint32_t submitCount, const VkSubmitInfo2 * /* Only consider queue events on graphics/compute when enabled. */ if (!device->sqtt_enabled || !radv_sqtt_queue_events_enabled() || !is_gfx_or_ace) - return queue->device->layer_dispatch.rgp.QueueSubmit2KHR(_queue, submitCount, pSubmits, _fence); + return queue->device->layer_dispatch.rgp.QueueSubmit2(_queue, submitCount, pSubmits, _fence); for (uint32_t i = 0; i < submitCount; i++) { const VkSubmitInfo2 *pSubmit = &pSubmits[i]; @@ -844,7 +844,7 @@ sqtt_QueueSubmit2KHR(VkQueue _queue, uint32_t submitCount, const VkSubmitInfo2 * sqtt_submit.commandBufferInfoCount = new_cmdbuf_count; sqtt_submit.pCommandBufferInfos = new_cmdbufs; - result = queue->device->layer_dispatch.rgp.QueueSubmit2KHR(_queue, 1, &sqtt_submit, _fence); + result = queue->device->layer_dispatch.rgp.QueueSubmit2(_queue, 1, &sqtt_submit, _fence); if (result != VK_SUCCESS) goto fail; diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 3485266eeab..9bf8636c273 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -607,7 +607,7 @@ radv_gang_barrier(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 src_ cmd_buffer->state.flush_bits & RADV_CMD_FLUSH_ALL_COMPUTE & ~RADV_CMD_FLAG_CS_PARTIAL_FLUSH; /* Add stage flush only when necessary. */ - if (src_stage_mask & (VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT | VK_PIPELINE_STAGE_2_TRANSFER_BIT | + if (src_stage_mask & (VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT | VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT)) cmd_buffer->gang.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH; @@ -618,7 +618,7 @@ radv_gang_barrier(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 src_ dst_stage_mask |= cmd_buffer->state.dma_is_busy ? VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT : 0; /* Increment the GFX/ACE semaphore when task shaders are blocked. */ - if (dst_stage_mask & (VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR | VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT | + if (dst_stage_mask & (VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT | VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT | VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT)) cmd_buffer->gang.sem.leader_value++; } diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index 602a9952d4b..e585090b453 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++ b/src/amd/vulkan/radv_descriptor_set.c @@ -90,7 +90,7 @@ radv_descriptor_alignment(VkDescriptorType type) } static bool -radv_mutable_descriptor_type_size_alignment(const VkMutableDescriptorTypeListVALVE *list, uint64_t *out_size, +radv_mutable_descriptor_type_size_alignment(const VkMutableDescriptorTypeListEXT *list, uint64_t *out_size, uint64_t *out_align) { uint32_t max_size = 0; @@ -910,7 +910,7 @@ radv_create_descriptor_pool(struct radv_device *device, const VkDescriptorPoolCr } if (bo_size) { - if (!(pCreateInfo->flags & VK_DESCRIPTOR_POOL_CREATE_HOST_ONLY_BIT_VALVE)) { + if (!(pCreateInfo->flags & VK_DESCRIPTOR_POOL_CREATE_HOST_ONLY_BIT_EXT)) { enum radeon_bo_flag flags = RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT; if (device->instance->zero_vram)
