Module: Mesa
Branch: main
Commit: 2c427d7c20b88a7ee37448a8e871025b52833647
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c427d7c20b88a7ee37448a8e871025b52833647

Author: Faith Ekstrand <[email protected]>
Date:   Tue Dec  5 20:45:56 2023 -0600

nak: Implement usub_sat

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26535>

---

 src/nouveau/compiler/nak.rs          |  2 +-
 src/nouveau/compiler/nak_from_nir.rs | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/src/nouveau/compiler/nak.rs b/src/nouveau/compiler/nak.rs
index 929a4e40d5a..14780ef4925 100644
--- a/src/nouveau/compiler/nak.rs
+++ b/src/nouveau/compiler/nak.rs
@@ -127,7 +127,7 @@ fn nir_options(dev: &nv_device_info) -> 
nir_shader_compiler_options {
     op.lower_device_index_to_zero = true;
     op.lower_isign = true;
     op.lower_uadd_sat = dev.sm < 70;
-    op.lower_usub_sat = true; // TODO
+    op.lower_usub_sat = dev.sm < 70;
     op.lower_iadd_sat = true; // TODO
     op.use_interpolated_input_intrinsics = true;
     op.lower_int64_options = !(nir_lower_icmp64
diff --git a/src/nouveau/compiler/nak_from_nir.rs 
b/src/nouveau/compiler/nak_from_nir.rs
index 01636c5211d..ccc8a08169b 100644
--- a/src/nouveau/compiler/nak_from_nir.rs
+++ b/src/nouveau/compiler/nak_from_nir.rs
@@ -1066,6 +1066,39 @@ impl<'a> ShaderFromNir<'a> {
                     b.sel(ovf_lo.into(), u32::MAX.into(), sum_lo.into())
                 }
             }
+            nir_op_usub_sat => {
+                let x = srcs[0].as_ssa().unwrap();
+                let y = srcs[1].as_ssa().unwrap();
+                let sum_lo = b.alloc_ssa(RegFile::GPR, 1);
+                let ovf_lo = b.alloc_ssa(RegFile::Pred, 1);
+                // The result of OpIAdd3X is the 33-bit value
+                //
+                //  s|o = x + !y + 1
+                //
+                // The overflow bit of this result is true if and only if the
+                // subtract did NOT overflow.
+                b.push_op(OpIAdd3 {
+                    dst: sum_lo.into(),
+                    overflow: [ovf_lo.into(), Dst::None],
+                    srcs: [0.into(), x[0].into(), Src::from(y[0]).ineg()],
+                });
+                if alu.def.bit_size() == 64 {
+                    let sum_hi = b.alloc_ssa(RegFile::GPR, 1);
+                    let ovf_hi = b.alloc_ssa(RegFile::Pred, 1);
+                    b.push_op(OpIAdd3X {
+                        dst: sum_hi.into(),
+                        overflow: [ovf_hi.into(), Dst::None],
+                        srcs: [0.into(), x[1].into(), Src::from(y[1]).bnot()],
+                        carry: [ovf_lo.into(), false.into()],
+                    });
+                    let lo = b.sel(ovf_hi.into(), sum_lo.into(), 0.into());
+                    let hi = b.sel(ovf_hi.into(), sum_hi.into(), 0.into());
+                    [lo[0], hi[0]].into()
+                } else {
+                    assert!(alu.def.bit_size() == 32);
+                    b.sel(ovf_lo.into(), sum_lo.into(), 0.into())
+                }
+            }
             nir_op_unpack_32_2x16_split_x => {
                 b.prmt(srcs[0], 0.into(), [0, 1, 4, 4])
             }

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