Module: Mesa Branch: main Commit: 79cf2b6824d49c3a00e8a747456790184f076e7d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=79cf2b6824d49c3a00e8a747456790184f076e7d
Author: Samuel Pitoiset <[email protected]> Date: Thu Nov 16 17:12:03 2023 +0100 radv: determine and emit SPI_SHADER_Z_FORMAT for PS epilogs Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413> --- src/amd/vulkan/radv_cmd_buffer.c | 3 +++ src/amd/vulkan/radv_pipeline_graphics.c | 7 ++++++- src/amd/vulkan/radv_shader.c | 2 ++ src/amd/vulkan/radv_shader.h | 3 +++ 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f26205836d7..f3bc4a134f5 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1858,6 +1858,9 @@ radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, ac_get_cb_shader_mask(ps_epilog->spi_shader_col_format)); + if (ps_epilog->spi_shader_z_format) + radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT, ps_epilog->spi_shader_z_format); + assert(ps_shader->config.num_shared_vgprs == 0); if (G_00B848_VGPRS(ps_epilog->rsrc1) > G_00B848_VGPRS(ps_shader->config.rsrc1)) { uint32_t rsrc1 = ps_shader->config.rsrc1; diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 25b1361a352..303f597b886 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -1680,7 +1680,7 @@ struct radv_ps_epilog_key radv_generate_ps_epilog_key(const struct radv_device *device, const struct radv_ps_epilog_state *state, bool disable_mrt_compaction) { - unsigned col_format = 0, is_int8 = 0, is_int10 = 0, is_float32 = 0; + unsigned col_format = 0, is_int8 = 0, is_int10 = 0, is_float32 = 0, z_format = 0; struct radv_ps_epilog_key key; memset(&key, 0, sizeof(key)); @@ -1733,6 +1733,10 @@ radv_generate_ps_epilog_key(const struct radv_device *device, const struct radv_ col_format |= (col_format & 0xf) << 4; } + if (state->alpha_to_coverage_via_mrtz) + z_format = ac_get_spi_shader_z_format(state->export_depth, state->export_stencil, state->export_sample_mask, + state->alpha_to_coverage_via_mrtz); + key.spi_shader_col_format = col_format; key.color_is_int8 = device->physical_device->rad_info.gfx_level < GFX8 ? is_int8 : 0; key.color_is_int10 = device->physical_device->rad_info.gfx_level < GFX8 ? is_int10 : 0; @@ -1742,6 +1746,7 @@ radv_generate_ps_epilog_key(const struct radv_device *device, const struct radv_ key.export_stencil = state->export_stencil; key.export_sample_mask = state->export_sample_mask; key.alpha_to_coverage_via_mrtz = state->alpha_to_coverage_via_mrtz; + key.spi_shader_z_format = z_format; return key; } diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index de1391ffd59..05e19dc0aea 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -2190,6 +2190,7 @@ radv_shader_part_create(struct radv_device *device, struct radv_shader_part_bina shader_part->disasm_string = binary->disasm_size ? strdup((const char *)(binary->data + binary->code_size)) : NULL; shader_part->spi_shader_col_format = binary->info.spi_shader_col_format; + shader_part->spi_shader_z_format = binary->info.spi_shader_z_format; /* Allocate memory and upload. */ shader_part->alloc = radv_alloc_shader_memory(device, shader_part->code_size, false, NULL); @@ -2702,6 +2703,7 @@ radv_create_ps_epilog(struct radv_device *device, const struct radv_ps_epilog_ke aco_compile_ps_epilog(&ac_opts, &ac_info, &ac_epilog_info, &args.ac, &radv_aco_build_shader_part, (void **)&binary); binary->info.spi_shader_col_format = key->spi_shader_col_format; + binary->info.spi_shader_z_format = key->spi_shader_z_format; epilog = radv_shader_part_create(device, binary, info.wave_size); if (!epilog) diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index b8acd184f9a..e7b17a1788f 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -67,6 +67,7 @@ struct radv_shader_stage_key { struct radv_ps_epilog_key { uint32_t spi_shader_col_format; + uint32_t spi_shader_z_format; /* Bitmasks, each bit represents one of the 8 MRTs. */ uint8_t color_is_int8; @@ -555,6 +556,7 @@ struct radv_shader_binary_rtld { struct radv_shader_part_binary { struct { uint32_t spi_shader_col_format; + uint32_t spi_shader_z_format; } info; uint8_t num_sgprs; @@ -640,6 +642,7 @@ struct radv_shader_part { uint32_t rsrc1; bool nontrivial_divisors; uint32_t spi_shader_col_format; + uint32_t spi_shader_z_format; uint64_t upload_seq; /* debug only */
