Module: Mesa Branch: main Commit: db6aaa691d05ef017b803d11cce4e341d1a98882 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db6aaa691d05ef017b803d11cce4e341d1a98882
Author: Rohan Garg <[email protected]> Date: Thu Nov 30 20:30:39 2023 +0100 intel/compiler: infer the number of operands using lsc_op_num_data_values nir_emit_global_atomic should utilize lsc_op_num_data_values to infer the number of operands for global atomic ops, following the same pattern as nir_emit_surface_atomic Fixes: 90a2137 ('intel/compiler: Use LSC opcode enum rather than legacy BRW_AOPs') Signed-off-by: Rohan Garg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26432> --- src/intel/compiler/brw_fs_nir.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 13386ec40a1..e4f075353a6 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -6391,16 +6391,17 @@ fs_visitor::nir_emit_global_atomic(const fs_builder &bld, nir_intrinsic_instr *instr) { enum lsc_opcode op = lsc_aop_for_nir_intrinsic(instr); + int num_data = lsc_op_num_data_values(op); fs_reg dest = get_nir_def(instr->def); fs_reg addr = get_nir_src(instr->src[0]); fs_reg data; - if (op != LSC_OP_ATOMIC_INC && op != LSC_OP_ATOMIC_DEC) + if (num_data >= 1) data = expand_to_32bit(bld, get_nir_src(instr->src[1])); - if (op == LSC_OP_ATOMIC_CMPXCHG) { + if (num_data >= 2) { fs_reg tmp = bld.vgrf(data.type, 2); fs_reg sources[2] = { data,
