Module: Mesa Branch: main Commit: 5bfb46a735eca2c370c4992912fa25edd40a7537 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5bfb46a735eca2c370c4992912fa25edd40a7537
Author: Faith Ekstrand <[email protected]> Date: Thu Dec 7 11:28:01 2023 -0600 nak: Add dnz bits to OpFMul and OpFFma Also, while we're here, clean up the from_nir code a bit. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26572> --- src/nouveau/compiler/nak/builder.rs | 1 + src/nouveau/compiler/nak/encode_sm70.rs | 4 ++-- src/nouveau/compiler/nak/from_nir.rs | 12 ++++++------ src/nouveau/compiler/nak/ir.rs | 10 ++++++++-- 4 files changed, 17 insertions(+), 10 deletions(-) diff --git a/src/nouveau/compiler/nak/builder.rs b/src/nouveau/compiler/nak/builder.rs index 095b7e47bd7..cc1daacabb1 100644 --- a/src/nouveau/compiler/nak/builder.rs +++ b/src/nouveau/compiler/nak/builder.rs @@ -190,6 +190,7 @@ pub trait SSABuilder: Builder { saturate: false, rnd_mode: FRndMode::NearestEven, ftz: false, + dnz: false, }); dst } diff --git a/src/nouveau/compiler/nak/encode_sm70.rs b/src/nouveau/compiler/nak/encode_sm70.rs index 981f12ae94b..dceac382931 100644 --- a/src/nouveau/compiler/nak/encode_sm70.rs +++ b/src/nouveau/compiler/nak/encode_sm70.rs @@ -437,7 +437,7 @@ impl SM70Instr { ALUSrc::from_src(&op.srcs[1]), ALUSrc::from_src(&op.srcs[2]), ); - self.set_bit(76, false); /* TODO: DNZ */ + self.set_bit(76, op.dnz); self.set_bit(77, op.saturate); self.set_rnd_mode(78..80, op.rnd_mode); self.set_bit(80, op.ftz); @@ -463,7 +463,7 @@ impl SM70Instr { ALUSrc::from_src(&op.srcs[1]), ALUSrc::from_src(&Src::new_zero()), ); - self.set_bit(76, false); /* TODO: DNZ */ + self.set_bit(76, op.dnz); self.set_bit(77, op.saturate); self.set_rnd_mode(78..80, op.rnd_mode); self.set_bit(80, op.ftz); diff --git a/src/nouveau/compiler/nak/from_nir.rs b/src/nouveau/compiler/nak/from_nir.rs index bf760003bfa..873968b0e58 100644 --- a/src/nouveau/compiler/nak/from_nir.rs +++ b/src/nouveau/compiler/nak/from_nir.rs @@ -707,14 +707,14 @@ impl<'a> ShaderFromNir<'a> { let ftype = FloatType::from_bits(alu.def.bit_size().into()); assert!(alu.def.bit_size() == 32); let dst = b.alloc_ssa(RegFile::GPR, 1); - let ffma = OpFFma { + b.push_op(OpFFma { dst: dst.into(), srcs: [srcs[0], srcs[1], srcs[2]], saturate: self.try_saturate_alu_dst(&alu.def), rnd_mode: self.float_ctl[ftype].rnd_mode, ftz: self.float_ctl[ftype].ftz, - }; - b.push_op(ffma); + dnz: false, + }); dst } nir_op_flog2 => { @@ -736,14 +736,14 @@ impl<'a> ShaderFromNir<'a> { let ftype = FloatType::from_bits(alu.def.bit_size().into()); assert!(alu.def.bit_size() == 32); let dst = b.alloc_ssa(RegFile::GPR, 1); - let fmul = OpFMul { + b.push_op(OpFMul { dst: dst.into(), srcs: [srcs[0], srcs[1]], saturate: self.try_saturate_alu_dst(&alu.def), rnd_mode: self.float_ctl[ftype].rnd_mode, ftz: self.float_ctl[ftype].ftz, - }; - b.push_op(fmul); + dnz: false, + }); dst } nir_op_fquantize2f16 => { diff --git a/src/nouveau/compiler/nak/ir.rs b/src/nouveau/compiler/nak/ir.rs index 4e771977525..1f5a7030a61 100644 --- a/src/nouveau/compiler/nak/ir.rs +++ b/src/nouveau/compiler/nak/ir.rs @@ -2213,6 +2213,7 @@ pub struct OpFFma { pub saturate: bool, pub rnd_mode: FRndMode, pub ftz: bool, + pub dnz: bool, } impl DisplayOp for OpFFma { @@ -2224,7 +2225,9 @@ impl DisplayOp for OpFFma { if self.rnd_mode != FRndMode::NearestEven { write!(f, "{}", self.rnd_mode)?; } - if self.ftz { + if self.dnz { + write!(f, ".dnz")?; + } else if self.ftz { write!(f, ".ftz")?; } write!(f, " {} {} {}", self.srcs[0], self.srcs[1], self.srcs[2]) @@ -2269,6 +2272,7 @@ pub struct OpFMul { pub saturate: bool, pub rnd_mode: FRndMode, pub ftz: bool, + pub dnz: bool, } impl DisplayOp for OpFMul { @@ -2280,7 +2284,9 @@ impl DisplayOp for OpFMul { if self.rnd_mode != FRndMode::NearestEven { write!(f, "{}", self.rnd_mode)?; } - if self.ftz { + if self.dnz { + write!(f, ".dnz")?; + } else if self.ftz { write!(f, ".ftz")?; } write!(f, " {} {}", self.srcs[0], self.srcs[1],)
