Module: Mesa
Branch: main
Commit: 3955e596df06f4f1b904d932b61520154f6c5389
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3955e596df06f4f1b904d932b61520154f6c5389

Author: Faith Ekstrand <[email protected]>
Date:   Thu Dec  7 09:35:38 2023 -0600

nak: Implement fmulz and ffmaz

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10261
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26569>

---

 src/nouveau/compiler/nak/api.rs      | 4 ++++
 src/nouveau/compiler/nak/from_nir.rs | 8 ++++----
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/nouveau/compiler/nak/api.rs b/src/nouveau/compiler/nak/api.rs
index 1c1bf72e776..2af94814505 100644
--- a/src/nouveau/compiler/nak/api.rs
+++ b/src/nouveau/compiler/nak/api.rs
@@ -123,6 +123,10 @@ fn nir_options(dev: &nv_device_info) -> 
nir_shader_compiler_options {
     op.has_sudot_4x8 = dev.sm >= 70;
     op.max_unroll_iterations = 32;
 
+    // We set .ftz on f32 by default so we can support fmulz whenever the 
client
+    // doesn't explicitly request denorms.
+    op.has_fmulz_no_denorms = true;
+
     op
 }
 
diff --git a/src/nouveau/compiler/nak/from_nir.rs 
b/src/nouveau/compiler/nak/from_nir.rs
index 3bf58881478..1ca331ca603 100644
--- a/src/nouveau/compiler/nak/from_nir.rs
+++ b/src/nouveau/compiler/nak/from_nir.rs
@@ -703,7 +703,7 @@ impl<'a> ShaderFromNir<'a> {
                 dst
             }
             nir_op_fexp2 => b.mufu(MuFuOp::Exp2, srcs[0]),
-            nir_op_ffma => {
+            nir_op_ffma | nir_op_ffmaz => {
                 let ftype = FloatType::from_bits(alu.def.bit_size().into());
                 assert!(alu.def.bit_size() == 32);
                 let dst = b.alloc_ssa(RegFile::GPR, 1);
@@ -713,7 +713,7 @@ impl<'a> ShaderFromNir<'a> {
                     saturate: self.try_saturate_alu_dst(&alu.def),
                     rnd_mode: self.float_ctl[ftype].rnd_mode,
                     ftz: self.float_ctl[ftype].ftz,
-                    dnz: false,
+                    dnz: alu.op == nir_op_ffmaz,
                 });
                 dst
             }
@@ -732,7 +732,7 @@ impl<'a> ShaderFromNir<'a> {
                 });
                 dst
             }
-            nir_op_fmul => {
+            nir_op_fmul | nir_op_fmulz => {
                 let ftype = FloatType::from_bits(alu.def.bit_size().into());
                 assert!(alu.def.bit_size() == 32);
                 let dst = b.alloc_ssa(RegFile::GPR, 1);
@@ -742,7 +742,7 @@ impl<'a> ShaderFromNir<'a> {
                     saturate: self.try_saturate_alu_dst(&alu.def),
                     rnd_mode: self.float_ctl[ftype].rnd_mode,
                     ftz: self.float_ctl[ftype].ftz,
-                    dnz: false,
+                    dnz: alu.op == nir_op_fmulz,
                 });
                 dst
             }

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