Module: Mesa Branch: main Commit: 2701e634c1f164e5869b347b7e6806d054cd8577 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2701e634c1f164e5869b347b7e6806d054cd8577
Author: Karol Herbst <kher...@redhat.com> Date: Sun Dec 10 18:16:46 2023 +0100 nak: fix some sm checks for volta Signed-off-by: Karol Herbst <kher...@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26214> --- src/nouveau/compiler/nak/api.rs | 2 +- src/nouveau/compiler/nak/builder.rs | 4 ++-- src/nouveau/compiler/nak/encode_sm70.rs | 2 +- src/nouveau/compiler/nak/ir.rs | 9 +++++---- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/nouveau/compiler/nak/api.rs b/src/nouveau/compiler/nak/api.rs index 2af94814505..2979ae66974 100644 --- a/src/nouveau/compiler/nak/api.rs +++ b/src/nouveau/compiler/nak/api.rs @@ -285,7 +285,7 @@ pub extern "C" fn nak_compile_shader( let info = nak_shader_info { stage: nir.info.stage(), - num_gprs: if s.info.sm >= 75 { + num_gprs: if s.info.sm >= 70 { max(4, s.info.num_gprs + 2) } else { max(4, s.info.num_gprs) diff --git a/src/nouveau/compiler/nak/builder.rs b/src/nouveau/compiler/nak/builder.rs index 2f75410200e..bd1bd7a116e 100644 --- a/src/nouveau/compiler/nak/builder.rs +++ b/src/nouveau/compiler/nak/builder.rs @@ -295,7 +295,7 @@ pub trait SSABuilder: Builder { fn imul(&mut self, x: Src, y: Src) -> SSARef { let dst = self.alloc_ssa(RegFile::GPR, 1); - if self.sm() > 70 { + if self.sm() >= 70 { self.push_op(OpIMad { dst: dst.into(), srcs: [x, y, 0.into()], @@ -314,7 +314,7 @@ pub trait SSABuilder: Builder { fn imul_2x32_64(&mut self, x: Src, y: Src, signed: bool) -> SSARef { let dst = self.alloc_ssa(RegFile::GPR, 2); - if self.sm() > 70 { + if self.sm() >= 70 { self.push_op(OpIMad64 { dst: dst.into(), srcs: [x, y, 0.into()], diff --git a/src/nouveau/compiler/nak/encode_sm70.rs b/src/nouveau/compiler/nak/encode_sm70.rs index c120cc281ff..9d08492f464 100644 --- a/src/nouveau/compiler/nak/encode_sm70.rs +++ b/src/nouveau/compiler/nak/encode_sm70.rs @@ -1923,7 +1923,7 @@ impl SM70Instr { ip: usize, labels: &HashMap<Label, usize>, ) -> [u32; 4] { - assert!(sm >= 75); + assert!(sm >= 70); let mut si = SM70Instr { inst: [0; 4], diff --git a/src/nouveau/compiler/nak/ir.rs b/src/nouveau/compiler/nak/ir.rs index ba2dd97aa8b..d4cd742e8c6 100644 --- a/src/nouveau/compiler/nak/ir.rs +++ b/src/nouveau/compiler/nak/ir.rs @@ -138,9 +138,10 @@ impl RegFile { // We need at least 16 registers to satisfy RA constraints // for texture ops and another 2 for parallel copy lowering 18 - } else if sm >= 75 { - // Turing+ has a maximum of 253 registers. Presumably - // because two registers get burned for UGPRs? + } else if sm >= 70 { + // Volta+ has a maximum of 253 registers. Presumably + // because two registers get burned for UGPRs? Unclear + // on why we need it on Volta though. 253 } else { 255 @@ -5637,7 +5638,7 @@ impl Shader { self.map_instrs(|mut instr: Box<Instr>, _| -> MappedInstrs { match instr.op { Op::INeg(neg) => { - if sm >= 75 { + if sm >= 70 { instr.op = Op::IAdd3(OpIAdd3 { dst: neg.dst, overflow: [Dst::None; 2],
