Module: Mesa Branch: main Commit: de3190d36d7d7de95b5f08bac0d5d551df281efd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de3190d36d7d7de95b5f08bac0d5d551df281efd
Author: Karol Herbst <kher...@redhat.com> Date: Tue Dec 12 21:07:56 2023 +0100 radeonsi: fix reg_saved_mask for non graphics contexts The old code used to clear the bits, the new one set it. It should have used `BITSET_CLEAR_RANGE` instead. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10286 Fixes: 17e01a9a9b7 ("radeonsi: merge context_reg_saved_mask and other_reg_saved_mask into a BITSET") Signed-off-by: Karol Herbst <kher...@redhat.com> Reviewed-by: Marek Olšák <marek.ol...@amd.com> Reviewed-by: Michel Dänzer <mdaen...@redhat.com> Tested-by: Michel Dänzer <mdaen...@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26657> --- src/gallium/drivers/radeonsi/si_compute.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 092b3e3038d..7f62d80b0c5 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -1000,8 +1000,8 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info /* Skipping setting redundant registers on compute queues breaks compute. */ if (!sctx->has_graphics) { - BITSET_SET_RANGE(sctx->tracked_regs.reg_saved_mask, - SI_FIRST_TRACKED_OTHER_REG, SI_NUM_ALL_TRACKED_REGS - 1); + BITSET_CLEAR_RANGE(sctx->tracked_regs.reg_saved_mask, + SI_FIRST_TRACKED_OTHER_REG, SI_NUM_ALL_TRACKED_REGS - 1); } /* First emit registers. */
