Module: Mesa
Branch: main
Commit: 135a7d50311fe8c77df1a1d5068b111cca03ac10
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=135a7d50311fe8c77df1a1d5068b111cca03ac10

Author: Sagar Ghuge <sagar.gh...@intel.com>
Date:   Tue Nov 28 15:37:54 2023 -0800

iris: Handle aux map init for copy engine

We don't setup any state for the copy engine but platforms that supports
aux map, we need to init the aux map at context creation in order to
support compression.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9231

Signed-off-by: Sagar Ghuge <sagar.gh...@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26409>

---

 src/gallium/drivers/iris/iris_context.c |  1 +
 src/gallium/drivers/iris/iris_screen.h  |  1 +
 src/gallium/drivers/iris/iris_state.c   | 43 +++++++++++++++++++++++++++------
 3 files changed, 38 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_context.c 
b/src/gallium/drivers/iris/iris_context.c
index b8c4263f47d..82cdd54f365 100644
--- a/src/gallium/drivers/iris/iris_context.c
+++ b/src/gallium/drivers/iris/iris_context.c
@@ -376,6 +376,7 @@ iris_create_context(struct pipe_screen *pscreen, void 
*priv, unsigned flags)
 
    screen->vtbl.init_render_context(&ice->batches[IRIS_BATCH_RENDER]);
    screen->vtbl.init_compute_context(&ice->batches[IRIS_BATCH_COMPUTE]);
+   screen->vtbl.init_copy_context(&ice->batches[IRIS_BATCH_BLITTER]);
 
    if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
       return ctx;
diff --git a/src/gallium/drivers/iris/iris_screen.h 
b/src/gallium/drivers/iris/iris_screen.h
index 11277535642..a6c4b5d0c3d 100644
--- a/src/gallium/drivers/iris/iris_screen.h
+++ b/src/gallium/drivers/iris/iris_screen.h
@@ -63,6 +63,7 @@ struct iris_vtable {
    void (*destroy_state)(struct iris_context *ice);
    void (*init_render_context)(struct iris_batch *batch);
    void (*init_compute_context)(struct iris_batch *batch);
+   void (*init_copy_context)(struct iris_batch *batch);
    void (*upload_render_state)(struct iris_context *ice,
                                struct iris_batch *batch,
                                const struct pipe_draw_info *draw,
diff --git a/src/gallium/drivers/iris/iris_state.c 
b/src/gallium/drivers/iris/iris_state.c
index 7ed20054975..02fb1d97ac9 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1430,6 +1430,18 @@ iris_init_compute_context(struct iris_batch *batch)
    iris_batch_sync_region_end(batch);
 }
 
+static void
+iris_init_copy_context(struct iris_batch *batch)
+{
+   iris_batch_sync_region_start(batch);
+
+#if GFX_VER >= 12
+   init_aux_map_state(batch);
+#endif
+
+   iris_batch_sync_region_end(batch);
+}
+
 struct iris_vertex_buffer_state {
    /** The VERTEX_BUFFER_STATE hardware structure. */
    uint32_t state[GENX(VERTEX_BUFFER_STATE_length)];
@@ -6195,14 +6207,30 @@ init_aux_map_state(struct iris_batch *batch)
    uint64_t base_addr = intel_aux_map_get_base(aux_map_ctx);
    assert(base_addr != 0 && align64(base_addr, 32 * 1024) == base_addr);
 
-   bool use_compute_reg = batch->name == IRIS_BATCH_COMPUTE &&
-                          devinfo->has_compute_engine &&
-                          debug_get_bool_option("INTEL_COMPUTE_CLASS", false);
-
-   uint32_t reg = use_compute_reg ? GENX(COMPCS0_AUX_TABLE_BASE_ADDR_num) :
-                                    GENX(GFX_AUX_TABLE_BASE_ADDR_num);
+   uint32_t reg = 0;
+   switch (batch->name) {
+   case IRIS_BATCH_COMPUTE:
+      if (devinfo->has_compute_engine &&
+          debug_get_bool_option("INTEL_COMPUTE_CLASS", false)) {
+         reg = GENX(COMPCS0_AUX_TABLE_BASE_ADDR_num);
+         break;
+      }
+      /* fallthrough */
+      FALLTHROUGH;
+   case IRIS_BATCH_RENDER:
+      reg = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
+      break;
+   case IRIS_BATCH_BLITTER:
+#if GFX_VERx10 >= 125
+      reg = GENX(BCS_AUX_TABLE_BASE_ADDR_num);
+#endif
+      break;
+   default:
+      unreachable("Invalid batch for aux map init.");
+   }
 
-   iris_load_register_imm64(batch, reg, base_addr);
+   if (reg)
+      iris_load_register_imm64(batch, reg, base_addr);
 }
 #endif
 
@@ -9875,6 +9903,7 @@ genX(init_screen_state)(struct iris_screen *screen)
    screen->vtbl.destroy_state = iris_destroy_state;
    screen->vtbl.init_render_context = iris_init_render_context;
    screen->vtbl.init_compute_context = iris_init_compute_context;
+   screen->vtbl.init_copy_context = iris_init_copy_context;
    screen->vtbl.upload_render_state = iris_upload_render_state;
    screen->vtbl.upload_indirect_render_state = 
iris_upload_indirect_render_state;
    screen->vtbl.update_binder_address = iris_update_binder_address;

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