URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=69cc72e50adcf110e0cbffb75acb487a3da00c18
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:54:17 2022 -0700
anv/gfx12: Hook up dual-SIMD8 fragment shader dispatch.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ec54e84da603fe9f4d0c2cb070284ce2a300403
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:54:11 2022 -0700
iris/gfx12: Hook up dual-SIMD8 fragment shader dispatch.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ccb5795938c1b0870530798c6d542b3f43c82c32
Author: Francisco Jerez <[email protected]>
Date: Thu Nov 30 20:48:29 2023 -0800
intel/gfx12: Enable SIMD8 dispatch in 3DSTATE_PS for FS multipolygon
dispatch.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4868408e6e02e54cc49504f69c25e72bda346faf
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:41:16 2022 -0700
intel/genxml: Add 3DSTATE_PS definitions needed for dual-SIMD8 dispatch on
Gfx12+.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f2c44dc21719eb4cf5c383866c897fd73956d2f
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:32:57 2022 -0700
intel/compiler: Attempt to build dual-SIMD8 variant of fragment shaders on
gfx12+ platforms.
Similar to other FS dispatch modes, attempt to build a dual-SIMD8
program if the regular SIMD8 program didn't spill and doubling the
amount of space for varyings doesn't cause us to go over the thread
payload limit. Dual-SIMD8 builds in combination with coarse pixel
shading are currently not handled.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=261d07f3989738540764f88b57b7c402ed057a7f
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:40:23 2022 -0700
intel: Add debug flag for enabling dual-SIMD8 fragment shader dispatch.
Note that this option isn't enabled by default yet pending additional
performance evaluation.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=28aec45eed56b20b3155a646d00d046c128c798e
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 17:05:44 2022 -0700
intel/fs/gfx12: Implement multi-polygon format of render target array index
in PS payload.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b1ab77423e64397c700cda7c9ed0de273881162
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 17:02:27 2022 -0700
intel/fs/gfx12: Implement multi-polygon format of back/front-facing flag in
PS payload.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4672fcbc76b1e2d02810cd95584fcfa72f774b47
Author: Francisco Jerez <[email protected]>
Date: Sat Jun 11 17:35:00 2022 -0700
intel/fs: Fix PS thread payload setup for depth_w_coef_reg.
It's not replicated per SIMD16 half of a SIMD32 thread on the PS
payload. Make fs_visitor::payload::depth_w_coef_reg a scalar rather
than an array.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09ea8409870910b7f08000c4bf9081b939cd1d72
Author: Francisco Jerez <[email protected]>
Date: Thu Dec 7 20:00:31 2023 -0800
intel/fs: No need to copy null destinations in lower_simd_width.
The copy would be discarded immediately. Until now we were relying on
DCE to eliminate these, but it seems like in some cases MOVs into the
null register emitted by lower_simd_width() are never eliminated,
likely because a lower_simd_width() call has been introduced close to
the bottom of optimize() which isn't follow by any additional DCE
passes.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e0760a993faf9d81bc7d5c8ffbe34d95e4c034c
Author: Francisco Jerez <[email protected]>
Date: Thu Dec 7 19:38:02 2023 -0800
intel/fs/gfx12: Don't consider multipolygon PS to have packed dispatch.
This fixes a number of regressions and hangs in multipolygon fragment
shaders that have FIND_LIVE_CHANNEL sequences which would otherwise
lead to access of a dead channel. Note that the failures don't seem
to be reproducible in simulation.
Acked-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f92baa5d31d69e79139650b2468b996338dfd6f
Author: Francisco Jerez <[email protected]>
Date: Thu Dec 7 19:26:22 2023 -0800
intel/fs/gfx12+: Don't set nir_divergence_single_prim_per_subgroup option
for fragment shaders.
Flat-shaded inputs and other per-primitive values can no longer be
considered to be uniform across fragment shader subgroups due to
multipolygon dispatch.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bf99e6a452beefd18772934988fe0d6b86f74fc
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:17:21 2022 -0700
intel/compiler: Don't change types for copies from ATTR file.
Since the <8;8,0> regions they use in multipolygon mode could violate
regioning restrictions in some cases, depending on the execution type
of the instruction. Note that the assertion is removed from
try_copy_propagate() since a more accurate check is used within that
function than what fs_inst::can_change_types() can do.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ed36050fb9b5b890c69ae55c3efbef62e7e5e60
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:35:59 2022 -0700
intel/fs: Don't copy-propagate ATTR registers in multi-polygon FS shaders
when invalid.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f89fa63e6c0f0a34fc5925000e2eb12bd02e6cf
Author: Jordan Justen <[email protected]>
Date: Thu Sep 21 13:55:41 2023 -0700
intel/compiler: Pass max_polygons to copy-prop from fs_visitor.
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b62ad4e0288a11898b425ef9594789f345f76c4b
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:22:40 2022 -0700
intel/fs: Rework layout of FS vertex setup data in ATTR file to support
multi-polygon dispatch.
The updated layout includes one copy of each plane parameter per
channel of the SIMD thread, in order to allow channels to process
different polygons.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a844c0b185bffc7846eb1b4810fd8facf9b2a0ef
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:18:13 2022 -0700
intel/fs: Fix fs_reg::component_size() to handle two-dimensional register
regions.
Add code to calculate the size in bytes of arbitrary two-dimensional
regions for FIXED_GRF and ARF registers.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=83a0252e8d45f74f9ccc881db8cfc3e9e4470b06
Author: Francisco Jerez <[email protected]>
Date: Thu Dec 7 20:07:25 2023 -0800
intel/fs: Pass builder to per_primitive_reg().
Matches prototype of interp_reg(), will be useful in a subsequent commit.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e9f09dbe52242dee2c734903ab197691e195f35
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:19:05 2022 -0700
intel/fs: Provide component index explicitly to interp_reg().
Main motivation is that for multipolygon PS shaders the i-th plane
parameter for the j-th input attribute will no longer necessarily be a
scalar, since different channels may be processing different polygons
with different input plane parameters, so simply taking a component()
of the result of interp_reg() will no longer work. Instead of
duplicating the multipolygon handling logic in every caller of
interp_reg(), fold the component() call into interp_reg() so we can
replace it with multipolygon-correct code more easily.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=742a575bd6f6281a2780ee50a0a29f01bae10e30
Author: Francisco Jerez <[email protected]>
Date: Mon Sep 12 16:48:45 2022 -0700
intel/fs: Consider ATTR registers with different fs_reg::nr as belonging to
disjoint register spaces.
Instead of treating fs_reg::nr as an offset for ATTR registers simply
consider different indices as denoting disjoint spaces that can never
be accessed simultaneously by a single region. From now on geometry
stages will just use ATTR #0 for everything and select specific
attributes via offset() with the native dispatch width of the program,
which should work on current platforms as well as on Xe2+. See
"intel/fs: Map all GS input attributes to ATTR register number 0." for
the rationale.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d26ed66881f07c2f9490e0865fc806a3d3f719d
Author: Francisco Jerez <[email protected]>
Date: Mon Sep 12 16:49:11 2022 -0700
intel/fs: Assert fs_reg::nr is always zero for ATTR registers in geometry
stages.
Instead of treating fs_reg::nr as an offset for ATTR registers simply
consider different indices as denoting disjoint spaces that can never
be accessed simultaneously by a single region. From now on geometry
stages will just use ATTR #0 for everything and select specific
attributes via offset() with the native dispatch width of the program,
which should work on current platforms as well as on Xe2+. See
"intel/fs: Map all GS input attributes to ATTR register number 0." for
the rationale.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b26cf8b1891b820da10c74eef9298a637e75a976
Author: Francisco Jerez <[email protected]>
Date: Mon Sep 12 16:48:02 2022 -0700
intel/fs: Map all TES input attributes to ATTR register number 0.
Instead of treating fs_reg::nr as an offset for ATTR registers simply
consider different indices as denoting disjoint spaces that can never
be accessed simultaneously by a single region. From now on geometry
stages will just use ATTR #0 for everything and select specific
attributes via offset() with the native dispatch width of the program,
which should work on current platforms as well as on Xe2+. See
"intel/fs: Map all GS input attributes to ATTR register number 0." for
the rationale.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef12565a378848ad9a65621ea01d66c1719859cf
Author: Francisco Jerez <[email protected]>
Date: Mon Sep 12 16:47:19 2022 -0700
intel/fs: Map all VS input attributes to ATTR register number 0.
Instead of treating fs_reg::nr as an offset for ATTR registers simply
consider different indices as denoting disjoint spaces that can never
be accessed simultaneously by a single region. From now on geometry
stages will just use ATTR #0 for everything and select specific
attributes via offset() with the native dispatch width of the program,
which should work on current platforms as well as on Xe2+. See
"intel/fs: Map all GS input attributes to ATTR register number 0." for
the rationale.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d22721b5a6bebfa627ded44422a9df25bb033cc
Author: Francisco Jerez <[email protected]>
Date: Mon Sep 12 16:46:57 2022 -0700
intel/fs: Map all GS input attributes to ATTR register number 0.
The fs_reg::nr field currently has a somewhat inconsistent meaning for
ATTR registers depending on the shader stage. In geometry stages it
has a similar effect as fs_reg::offset except it's expressed in 32B
units instead of B units. In the PS however it's expressed in units
of logical scalar attributes (16B on present platforms), which isn't
currently handled correctly throughout the back-end since some places
assume 32B units in all cases.
The different format of the PS setup data in multi-polygon dispatch
modes would make its behavior even more irregular, which would be
worsened further (for both geometry and pixel stages) by the register
size changes coming up on Xe2, particularly in brw_ir_fs.h helpers
where neither the devinfo struct nor the shader stage are available.
Instead of treating it as an offset simply consider different
fs_reg::nr indices as denoting disjoint spaces that can never be
accessed simultaneously by a single region. From now on geometry
stages will just use ATTR #0 for everything and select specific
attributes via offset() with the native dispatch width of the program,
which should work on current platforms as well as on Xe2+.
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4aca2ebaa75328dc216693f4f23d1161b2fd250
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:31:00 2022 -0700
intel/fs: Add separate constructor of fs_visitor for fragment shaders.
To allow specifying the number of polygons that will be processed per
SIMD thread.
Rework:
* Jordan: Add needs_register_pressure following
09cdb77a92f ("intel/fs: report max register pressure in shader stats")
Reviewed-by: Jordan Justen <[email protected]>
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1eff2fcb6252a7086f6c8819c9f2f3ab126483cd
Author: Francisco Jerez <[email protected]>
Date: Thu Dec 7 19:47:55 2023 -0800
intel/compiler: Add polygon count statistic to brw_compile_stats.
And use it in ANV in order to return a "SIMDNxM" name from
vkGetPipelineExecutablePropertiesKHR.
Reviewed-by: Jordan Justen <[email protected]>
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ccf9174655c96f8cdb208ed349a9934de4d7dcec
Author: Francisco Jerez <[email protected]>
Date: Tue Jun 28 17:44:13 2022 -0700
intel/compiler: Add multipolygon dispatch fields to brw_wm_prog_data.
Add fields that track the number of polygons processed per PS SIMD
thread (note that this might be lower than the value that was
specified to the compiler via brw_compile_fs_params if compilation at
the desired polygon count wasn't possible), and the dispatch width of
the multi-polygon PS kernel.
Reviewed-by: Jordan Justen <[email protected]>
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7b1993376503a6922125cc7fec32b1ce5dc16cf
Author: Francisco Jerez <[email protected]>
Date: Wed Jun 22 16:16:08 2022 -0700
intel/compiler: Add max_polygons FS compilation parameter.
Add a brw_compile_fs_params parameter that specifies to the compiler
the maximum number of polygons that may be processed in parallel per
PS SIMD thread.
Reviewed-by: Jordan Justen <[email protected]>
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
