Mesa (main): intel/fs/xe2+: Stop building SIMD8 shaders for geometry stages (VS/TCS/TES/GS).

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Module: Mesa
Branch: main
Commit: 3f92dde55efeae8b692780602008b72821900c8b
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f92dde55efeae8b692780602008b72821900c8b

Author: Francisco Jerez <curroje...@riseup.net>
Date:   Fri Dec  1 20:40:45 2023 -0800

intel/fs/xe2+: Stop building SIMD8 shaders for geometry stages (VS/TCS/TES/GS).

They are no longer suppored by the fixed-function hardware.

Reviewed-by: Caio Oliveira <caio.olive...@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605>

---

 src/intel/compiler/brw_fs_visitor.cpp | 2 +-
 src/intel/compiler/brw_shader.cpp     | 3 ++-
 src/intel/compiler/brw_vec4.cpp       | 3 ++-
 src/intel/compiler/brw_vec4_tcs.cpp   | 5 +++--
 4 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/intel/compiler/brw_fs_visitor.cpp 
b/src/intel/compiler/brw_fs_visitor.cpp
index 644f8396a89..2ba4fc29c4b 100644
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -1211,7 +1211,7 @@ fs_visitor::fs_visitor(const struct brw_compiler 
*compiler,
      live_analysis(this), regpressure_analysis(this),
      performance_analysis(this),
      needs_register_pressure(needs_register_pressure),
-     dispatch_width(8),
+     dispatch_width(compiler->devinfo->ver >= 20 ? 16 : 8),
      max_polygons(0),
      api_subgroup_size(brw_nir_api_subgroup_size(shader, dispatch_width))
 {
diff --git a/src/intel/compiler/brw_shader.cpp 
b/src/intel/compiler/brw_shader.cpp
index c0a266009b7..556c5a4d867 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -1365,8 +1365,9 @@ brw_compile_tes(const struct brw_compiler *compiler,
    }
 
    if (is_scalar) {
+      const unsigned dispatch_width = devinfo->ver >= 20 ? 16 : 8;
       fs_visitor v(compiler, &params->base, &key->base,
-                   &prog_data->base.base, nir, 8,
+                   &prog_data->base.base, nir, dispatch_width,
                    params->base.stats != NULL, debug_enabled);
       if (!v.run_tes()) {
          params->base.error_str =
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 634af11e137..993b1fa9c43 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2649,10 +2649,11 @@ brw_compile_vs(const struct brw_compiler *compiler,
    }
 
    if (is_scalar) {
+      const unsigned dispatch_width = compiler->devinfo->ver >= 20 ? 16 : 8;
       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
 
       fs_visitor v(compiler, &params->base, &key->base,
-                   &prog_data->base.base, nir, 8,
+                   &prog_data->base.base, nir, dispatch_width,
                    params->base.stats != NULL, debug_enabled);
       if (!v.run_vs()) {
          params->base.error_str =
diff --git a/src/intel/compiler/brw_vec4_tcs.cpp 
b/src/intel/compiler/brw_vec4_tcs.cpp
index 8a4c27087f6..c484177a8bc 100644
--- a/src/intel/compiler/brw_vec4_tcs.cpp
+++ b/src/intel/compiler/brw_vec4_tcs.cpp
@@ -447,9 +447,10 @@ brw_compile_tcs(const struct brw_compiler *compiler,
    }
 
    if (is_scalar) {
+      const unsigned dispatch_width = devinfo->ver >= 20 ? 16 : 8;
       fs_visitor v(compiler, &params->base, &key->base,
-                   &prog_data->base.base, nir, 8, params->base.stats != NULL,
-                   debug_enabled);
+                   &prog_data->base.base, nir, dispatch_width,
+                   params->base.stats != NULL, debug_enabled);
       if (!v.run_tcs()) {
          params->base.error_str =
             ralloc_strdup(params->base.mem_ctx, v.fail_msg);