Module: Mesa Branch: main Commit: 61c9cf9890431f94e3ec9c810aa18987fcfaafb3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=61c9cf9890431f94e3ec9c810aa18987fcfaafb3
Author: Danylo Piliaiev <[email protected]> Date: Thu Dec 28 19:04:26 2023 +0100 freedreno: Add a644 support The GPU is same as a660 but for SP_DBG_ECO_CNTL register value. Checked by comparing cmd streams between them. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10366 Signed-off-by: Danylo Piliaiev <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26836> --- src/freedreno/common/freedreno_devices.py | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py index 1b6c974791f..8661e90196a 100644 --- a/src/freedreno/common/freedreno_devices.py +++ b/src/freedreno/common/freedreno_devices.py @@ -675,6 +675,35 @@ add_gpus([ ) )) +add_gpus([ + GPUId(chip_id=0x6060201, name="FD644"), + ], A6xxGPUInfo( + CHIP.A6XX, + [a6xx_base, a6xx_gen4], + num_ccu = 3, + tile_align_w = 96, + tile_align_h = 16, + num_vsc_pipes = 32, + cs_shared_mem_size = 32 * 1024, + wave_granularity = 2, + fibers_per_sp = 128 * 4 * 16, + magic_regs = dict( + PC_POWER_CNTL = 2, + TPL1_DBG_ECO_CNTL = 0x05008000, + GRAS_DBG_ECO_CNTL = 0x0, + SP_CHICKEN_BITS = 0x00001400, + UCHE_CLIENT_PF = 0x00000084, + PC_MODE_CNTL = 0x1f, + SP_DBG_ECO_CNTL = 0x6, + RB_DBG_ECO_CNTL = 0x04100000, + RB_DBG_ECO_CNTL_blit = 0x04100000, + HLSQ_DBG_ECO_CNTL = 0x0, + RB_UNKNOWN_8E01 = 0x0, + VPC_DBG_ECO_CNTL = 0x02000000, + UCHE_UNKNOWN_0E12 = 0x00000001 + ) + )) + add_gpus([ GPUId(690), GPUId(chip_id=0xffff06090000, name="FD690"), # Default no-speedbin fallback
