Module: Mesa Branch: main Commit: 9e97ce59a849c05d50d417277a72ba0fd572cbc5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e97ce59a849c05d50d417277a72ba0fd572cbc5
Author: Sagar Ghuge <[email protected]> Date: Fri Oct 6 20:30:22 2023 -0700 anv: No need to emit PIPELINE_SELECT on Xe2+ On Xe2+, PIPELINE_SELECT is getting deprecated (Bspec 55860), as a result we don't have to do the stalling flushes while switching between different pipelines. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26637> --- src/intel/vulkan/genX_cmd_buffer.c | 13 ++++++++++++- src/intel/vulkan/genX_init_state.c | 14 ++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index e8b992d020a..469a15943e0 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -6818,6 +6818,8 @@ void genX(emit_pipeline_select)(struct anv_batch *batch, uint32_t pipeline, const struct anv_device *device) { + /* Bspec 55860: Xe2+ no longer requires PIPELINE_SELECT */ +#if GFX_VER < 20 anv_batch_emit(batch, GENX(PIPELINE_SELECT), ps) { ps.MaskBits = GFX_VERx10 >= 125 ? 0x93 : GFX_VER >= 12 ? 0x13 : 0x3; #if GFX_VER == 12 @@ -6833,6 +6835,7 @@ genX(emit_pipeline_select)(struct anv_batch *batch, uint32_t pipeline, device->vk.enabled_features.cooperativeMatrix; #endif } +#endif /* if GFX_VER < 20 */ } static void @@ -6844,6 +6847,14 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, if (cmd_buffer->state.current_pipeline == pipeline) return; +#if GFX_VER >= 20 + /* Since we are not stalling/flushing caches explicitly while switching + * between the pipelines, we need to apply data dependency flushes recorded + * previously on the resource. + */ + genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); +#else + #if GFX_VER == 9 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT: * @@ -6999,7 +7010,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, } } #endif - +#endif /* else of if GFX_VER >= 20 */ cmd_buffer->state.current_pipeline = pipeline; } diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c index f4892d687b4..b099f60981d 100644 --- a/src/intel/vulkan/genX_init_state.c +++ b/src/intel/vulkan/genX_init_state.c @@ -591,19 +591,33 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch) anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), zero); anv_batch_emit(&batch, GENX(3DSTATE_MESH_CONTROL), zero); anv_batch_emit(&batch, GENX(3DSTATE_TASK_CONTROL), zero); + + /* We no longer required to explicitly flush or invalidate caches since the + * PIPELINE_SELECT is getting deprecated on Xe2+. + */ +#if GFX_VER < 20 genx_batch_emit_pipe_control_write(&batch, device->info, _3D, NoWrite, ANV_NULL_ADDRESS, 0, ANV_PIPE_FLUSH_BITS | ANV_PIPE_INVALIDATE_BITS); +#endif + genX(emit_pipeline_select)(&batch, GPGPU, device); anv_batch_emit(&batch, GENX(CFE_STATE), cfe) { cfe.MaximumNumberofThreads = devinfo->max_cs_threads * devinfo->subslice_total; } + + /* We no longer required to explicitly flush or invalidate caches since the + * PIPELINE_SELECT is getting deprecated on Xe2+. + */ +#if GFX_VER < 20 genx_batch_emit_pipe_control_write(&batch, device->info, _3D, NoWrite, ANV_NULL_ADDRESS, 0, ANV_PIPE_FLUSH_BITS | ANV_PIPE_INVALIDATE_BITS); +#endif + genX(emit_pipeline_select)(&batch, _3D, device); #endif
