Module: Mesa Branch: main Commit: 4b30b46ffdbc962f09ef87529a71d78cf514f8d8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b30b46ffdbc962f09ef87529a71d78cf514f8d8
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Mon Jan 8 12:17:54 2024 +0200 intel/fs: fix depth compute state for unchanged depth layout There is no VK CTS exercising this case. If there was we would run into hangs as noticed in https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26876 Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Cc: mesa-stable Reviewed-by: Konstantin Seurer <konstantin.seu...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26923> --- src/intel/compiler/brw_fs.cpp | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index cde619e8e6f..cdf4db7a67f 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -7415,7 +7415,17 @@ computed_depth_mode(const nir_shader *shader) case FRAG_DEPTH_LAYOUT_LESS: return BRW_PSCDEPTH_ON_LE; case FRAG_DEPTH_LAYOUT_UNCHANGED: - return BRW_PSCDEPTH_OFF; + /* We initially set this to OFF, but having the shader write the + * depth means we allocate register space in the SEND message. The + * difference between the SEND register count and the OFF state + * programming makes the HW hang. + * + * Removing the depth writes also leads to test failures. So use + * LesserThanOrEqual, which fits writing the same value + * (unchanged/equal). + * + */ + return BRW_PSCDEPTH_ON_LE; } } return BRW_PSCDEPTH_OFF;
