Mesa (main): anv: Fix PAT entry for userptr in integrated GPUs

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Module: Mesa
Branch: main
Commit: 49fe060b5f39eb673b0c6a8757730386c6ce5570
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=49fe060b5f39eb673b0c6a8757730386c6ce5570

Author: José Roberto de Souza <jose.so...@intel.com>
Date:   Fri Jan 12 08:31:31 2024 -0800

anv: Fix PAT entry for userptr in integrated GPUs

Fixes: 060439bdf0e7 ("anv: Add ANV_BO_ALLOC_IMPORTED")
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27040>

---

 src/intel/vulkan/anv_device.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 97861da01b9..612caa5c553 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -5116,13 +5116,15 @@ const struct intel_device_info_pat_entry *
 anv_device_get_pat_entry(struct anv_device *device,
                          enum anv_bo_alloc_flags alloc_flags)
 {
+   if (alloc_flags & ANV_BO_ALLOC_IMPORTED)
+      return &device->info->pat.cached_coherent;
+
    /* PAT indexes has no actual effect in DG2 and DG1, smem caches will always
     * be snopped by GPU and lmem will always be WC.
     * This might change in future discrete platforms.
     */
    if (anv_physical_device_has_vram(device->physical)) {
-      if ((alloc_flags & ANV_BO_ALLOC_NO_LOCAL_MEM) ||
-          (alloc_flags & ANV_BO_ALLOC_IMPORTED))
+      if (alloc_flags & ANV_BO_ALLOC_NO_LOCAL_MEM)
          return &device->info->pat.cached_coherent;
       return &device->info->pat.writecombining;
    }