Module: Mesa Branch: master Commit: 9390af0d9636ed8e985ff22cdbbbf9b12c3a7586 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9390af0d9636ed8e985ff22cdbbbf9b12c3a7586
Author: Zou Nan hai <[email protected]> Date: Tue May 18 16:22:40 2010 +0800 i965: fix PIPE_CONTROL command for gen6. Signed-off-by: Zou Nan hai <[email protected]> Reviewed-by: Eric Anholt <[email protected]> --- src/mesa/drivers/dri/intel/intel_batchbuffer.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index de51340..446ce29 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -275,7 +275,16 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch) { struct intel_context *intel = batch->intel; - if (intel->gen >= 4) { + if (intel->gen >= 6) { + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH | + PIPE_CONTROL_WRITE_FLUSH | + PIPE_CONTROL_NO_WRITE); + OUT_BATCH(0); /* write address */ + OUT_BATCH(0); /* write data */ + ADVANCE_BATCH(); + } else if (intel->gen >= 4) { BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL | PIPE_CONTROL_WRITE_FLUSH | _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
