Module: Mesa
Branch: 9.0
Commit: 8b2922ff5aa68b5dca90d5b83d1e31da48b069b3
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b2922ff5aa68b5dca90d5b83d1e31da48b069b3

Author: Marek Olšák <[email protected]>
Date:   Fri Nov 23 00:38:44 2012 +0100

r600g: fix broken streamout if streamout_begin caused a context flush

This fixes graphics corruption in the case where the DISCARD_RANGE flag
is used to map a buffer.

NOTE: This is a candidate for the stable branches.
(cherry picked from commit cff4c948ed2708a6eb4b090ae87443a707cbd67f)

---

 src/gallium/drivers/r600/r600_hw_context.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index 5c9c21f..af27fd9 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1080,13 +1080,14 @@ void r600_context_streamout_begin(struct r600_context 
*ctx)
        unsigned *stride_in_dw = ctx->vs_shader->so.stride;
        unsigned buffer_en, i, update_flags = 0;
        uint64_t va;
+       unsigned num_cs_dw_streamout_end;
 
        buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
                    (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
                    (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
                    (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
 
-       ctx->num_cs_dw_streamout_end =
+       num_cs_dw_streamout_end =
                12 + /* flush_vgt_streamout */
                util_bitcount(buffer_en) * 8 + /* STRMOUT_BUFFER_UPDATE */
                3 /* set_streamout_enable(0) */;
@@ -1100,7 +1101,10 @@ void r600_context_streamout_begin(struct r600_context 
*ctx)
                           util_bitcount(buffer_en & 
ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
                           util_bitcount(buffer_en & 
~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
                           (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780 
? 2 : 0) + /* SURFACE_BASE_UPDATE */
-                          ctx->num_cs_dw_streamout_end, TRUE);
+                          num_cs_dw_streamout_end, TRUE);
+
+       /* This must be set after r600_need_cs_space. */
+       ctx->num_cs_dw_streamout_end = num_cs_dw_streamout_end;
 
        if (ctx->chip_class >= EVERGREEN) {
                evergreen_flush_vgt_streamout(ctx);

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