Module: Mesa
Branch: 9.2
Commit: e5ed198f35cddf1c47a69c72a540a5fb9d4adc33
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5ed198f35cddf1c47a69c72a540a5fb9d4adc33
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Thu Oct 24 00:32:52 2013 -0700
i965: Emit post-sync non-zero flush before 3DSTATE_GS_SVB_INDEX.
>From the comments above intel_emit_post_sync_nonzero_flush:
"[DevSNB-C+{W/A}] Before any depth stall flush (including those
produced by non-pipelined state commands), software needs to first
send a PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
This suggests that every non-pipelined (0x79xx) command needs a
post-sync non-zero flush before it.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Tested-by: Xinkai Chen <yeled.n...@gmail.com>
Reviewed-by: Eric Anholt <e...@anholt.net>
Cc: "9.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 436e815a250a8fde22d79093f4b9eed56472693b)
---
src/mesa/drivers/dri/i965/gen6_sol.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c
b/src/mesa/drivers/dri/i965/gen6_sol.c
index 5c294b1..fd6a314 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -153,6 +153,9 @@ brw_begin_transform_feedback(struct gl_context *ctx, GLenum
mode,
= _mesa_compute_max_transform_feedback_vertices(xfb_obj,
linked_xfb_info);
+ /* 3DSTATE_GS_SVB_INDEX is non-pipelined. */
+ intel_emit_post_sync_nonzero_flush(brw);
+
/* Initialize the SVBI 0 register to zero and set the maximum index. */
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
_______________________________________________
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-commit
