Module: Mesa Branch: master Commit: 35458a99c0940ec29503fa02134ec3ed9de363f9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=35458a99c0940ec29503fa02134ec3ed9de363f9
Author: Kenneth Graunke <[email protected]> Date: Wed Dec 11 15:25:58 2013 -0800 i965: Use full-length PIPE_CONTROL packets for workaround writes. I believe that PIPE_CONTROL uses the length field to decide whether to do 32-bit or 64-bit writes. A length of 4 would do a 32-bit write, while a length of 5 would do a 64-bit write. (I haven't verified this, though.) For workaround writes, we don't care what value gets written, or how much data. We're only writing something because hardware bugs mandate that do so. So using a 64-bit write should be fine. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Matt Turner <[email protected]> --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 12c7ecc..f54ca9b 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -493,12 +493,13 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw) { assert(brw->gen == 7); - BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); + BEGIN_BATCH(5); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_IMMEDIATE); OUT_RELOC(brw->batch.workaround_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BATCH(0); /* write data */ + OUT_BATCH(0); /* write data */ ADVANCE_BATCH(); } @@ -509,8 +510,8 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw) void gen7_emit_cs_stall_flush(struct brw_context *brw) { - BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); + BEGIN_BATCH(5); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2)); /* From p61 of the Ivy Bridge PRM (1.10.4 PIPE_CONTROL Command: DW1[20] * CS Stall): * @@ -528,6 +529,7 @@ gen7_emit_cs_stall_flush(struct brw_context *brw) OUT_RELOC(brw->batch.workaround_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BATCH(0); + OUT_BATCH(0); ADVANCE_BATCH(); } @@ -579,12 +581,13 @@ intel_emit_post_sync_nonzero_flush(struct brw_context *brw) PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD); - BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); + BEGIN_BATCH(5); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2)); OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); OUT_RELOC(brw->batch.workaround_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BATCH(0); /* write data */ + OUT_BATCH(0); /* write data */ ADVANCE_BATCH(); brw->batch.need_workaround_flush = false; _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
