Module: Mesa Branch: 10.3 Commit: 9a79018840accf6bd3a8b3c4e57e14d4a6e3ab27 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a79018840accf6bd3a8b3c4e57e14d4a6e3ab27
Author: Ilia Mirkin <imir...@alum.mit.edu> Date: Thu Sep 25 03:51:37 2014 -0400 gm107/ir: fix texture argument order Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu> Cc: "10.3" <mesa-sta...@lists.freedesktop.org> (cherry picked from commit 0532a5fd00cdddda0fd1727fb519cb4312f47e83) --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 32 +++++++++++++++++--- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 7 +++++ 2 files changed, 34 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index b3e1e69..31ff56c 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -607,6 +607,21 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) // lod bias // depth compare // offsets (same as fermi, except txd which takes it with array) + // + // Maxwell (tex): + // array + // coords + // indirect handle + // sample + // lod bias + // depth compare + // offsets + // + // Maxwell (txd): + // indirect handle + // coords + // array + offsets + // derivatives if (chipset >= NVISA_GK104_CHIPSET) { if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) { @@ -640,12 +655,17 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) const int sat = (i->op == OP_TXF) ? 1 : 0; DataType sTy = (i->op == OP_TXF) ? TYPE_U32 : TYPE_F32; bld.mkCvt(OP_CVT, TYPE_U16, layer, sTy, src)->saturate = sat; - for (int s = dim; s >= 1; --s) - i->setSrc(s, i->getSrc(s - 1)); - i->setSrc(0, layer); + if (i->op != OP_TXD || chipset < NVISA_GM107_CHIPSET) { + for (int s = dim; s >= 1; --s) + i->setSrc(s, i->getSrc(s - 1)); + i->setSrc(0, layer); + } else { + i->setSrc(dim, layer); + } } // Move the indirect reference to the first place - if (i->tex.rIndirectSrc >= 0) { + if (i->tex.rIndirectSrc >= 0 && ( + i->op == OP_TXD || chipset < NVISA_GM107_CHIPSET)) { Value *hnd = i->getIndirectR(); i->setIndirectR(NULL); @@ -748,8 +768,10 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) // create it if it's not already there, and INSBF it if it already // is. s = (i->tex.rIndirectSrc >= 0) ? 1 : 0; + if (chipset >= NVISA_GM107_CHIPSET) + s += dim; if (i->tex.target.isArray()) { - bld.mkOp3(OP_INSBF, TYPE_U32, i->getSrc(0), + bld.mkOp3(OP_INSBF, TYPE_U32, i->getSrc(s), bld.loadImm(NULL, imm), bld.mkImm(0xc10), i->getSrc(s)); } else { diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp index d47fed2..898653c 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp @@ -1921,6 +1921,13 @@ RegAlloc::InsertConstraintsPass::texConstraintGM107(TexInstruction *tex) if (isTextureOp(tex->op)) { if (tex->op != OP_TXQ) { s = tex->tex.target.getArgCount() - tex->tex.target.isMS(); + if (tex->op == OP_TXD) { + // Indirect handle belongs in the first arg + if (tex->tex.rIndirectSrc >= 0) + s++; + if (!tex->tex.target.isArray() && tex->tex.useOffsets) + s++; + } n = tex->srcCount(0xff) - s; } else { s = tex->srcCount(0xff); _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit