URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ddc25a8d4796316f0296eaa10eba26bd6dd1718
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Sep 26 16:08:52 2014 -0700
i965/fs: Properly calculate the number of instructions in
calculate_register_pressure
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=514fd1c55e617bb325979cbee4a89f0727c3b567
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Sep 12 16:17:37 2014 -0700
i965/fs: Use the GRF for FB writes on gen >= 7
On gen 7, the MRF was removed and we gained the ability to do send
instructions directly from the GRF. This commit enables that
functinoality for FB writes.
v2: Make handling of components more sane.
i965/fs: Force a high register for the final FB write
v2: Renamed the array for the range mappings and added a comment
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1dd9b90ecd8e001b40febfb8908c0b9a0c08c7d5
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Sep 16 16:28:53 2014 -0700
i965/fs: Handle COMPR4 in LOAD_PAYLOAD
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=29f4c5b5d5d142f19283c06e77bedd4b3793657a
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Sep 24 14:51:22 2014 -0700
i965/fs: Constant propagate into LOAD_PAYLOAD
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d770ce93aacf29940bacb6fe2ae78cf716751dc
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Sep 19 21:03:25 2014 -0700
i965/fs: Add split_virtual_grfs and compute_to_mrf after lower_load_payload
If we are going to use LOAD_PAYLOAD operations to fill MRF registers, then
we will need this.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b0e4b387a2aeb28e32df5b680013338a841859b
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Sep 16 15:16:20 2014 -0700
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction
Previously, we were use the base_mrf parameter of fs_inst to store the MRF
location. In preparation for doing FB writes from the GRF, we now also
allow you to set inst->base_mrf to -1 and provide a source register.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e1f52a6e2b0277de063a8d8b07c5e520795a23b
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Sep 11 16:43:37 2014 -0700
i965/fs: Use the GRF for UNTYPED_SURFACE_READ instructions
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d25aaf1cb1688b38b2a4025dbbff26d74291723c
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Sep 11 16:13:15 2014 -0700
i965/fs: Use the GRF for UNTYPED_ATOMIC instructions
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=65ddf6f40469c5da1e5daf4270ca698a03860472
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Sep 11 16:15:10 2014 -0700
i965/fs: Add a function for getting a component of a 8 or 16-wide register
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=30d718c2fbaeeffb24468ce773e44a6bf6f6aa2a
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Aug 29 17:22:57 2014 -0700
i965/fs: Use the instruction execution size directly for texture generation
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48ddd2889e15aaf8ddb6dff5d8b6dc275f7f3f8d
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Sep 16 18:02:52 2014 -0700
i965/fs: Use exec_size instead of force_uncompressed in dump_instruction
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b18fd234da275a0ec6b3c5cb77497a4c487c6366
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Sat Aug 16 11:34:56 2014 -0700
i965/fs: Use instruction execution sizes instead of heuristics
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=894ec5a1d819ed896395117303b1ff25be59ba75
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Aug 15 20:58:50 2014 -0700
i965/fs: Use instruction execution sizes to set compression state
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f1adb59659617a682988bc503b8a0a7077abb84
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Sep 4 20:40:34 2014 -0700
i965/fs: Remove unneeded uses of force_uncompressed
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2999f83bd987fd53e2348ceb887dc2d40096c813
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Sat Aug 16 11:38:07 2014 -0700
i965/fs: Derive force_uncompressed from instruction exec_size
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f41d052bf53e32761fb528f4be99a1af3a33ebc
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Sep 19 20:36:52 2014 -0700
i965/fs: Make fs_reg::effective_width take fs_inst* instead of fs_visitor*
Now that we have execution sizes, we can use that instead of the
dispatch width. This way it also works for 8-wide instructions in
SIMD16.
i965/fs: Make effective_width a variable instead of a function
i965/fs: Preserve effective width in constant propagation
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ba31cc000b096a3b1fe0e0a935a3ab2aa6803d2
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Sep 11 22:33:52 2014 -0700
i965/fs: Better guess the width of LOAD_PAYLOAD
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=071ac3a467479ce1ada1b86e2f65d4cc7d07753e
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Aug 14 13:56:24 2014 -0700
i965/fs: Add an exec_size field to fs_inst
This will, eventually, allow us to manage execution sizes of
instructions in a much more natural way from the fs_visitor level.
i965/fs: Explicitly set instruction execute size a couple of places
i965/blorp: Explicitly set instruction execute sizes
Since blorp is all 16-wide and nothing isn't, in general, very careful
about register width, we'll just set it all explicitly.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fbc0a798eef49c366437014134c59e16c39c7f95
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Aug 29 17:18:42 2014 -0700
i965/fs: Determine partial writes based on the destination width
Now that we track both halves of a 16-wide vgrf, we no longer need to worry
about force_sechalf or force_uncompressed. The only real issue is if the
destination is too small.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27d7ef094a55d6aeac22a11f20a9e819af4dd633
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Sep 16 16:34:23 2014 -0700
i965/fs: Fix a bug in register coalesce
This commit fixes a bug in register coalesce that happens when one register
is moved to another the proper number of times but the channels are
re-arranged. When this happens, the previous code would happily coalesce
the registers regardless of the fact that the channel mappins were wrong.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=16819b48ab0af244ccb5ef466a7343b1982792be
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Sep 18 12:16:25 2014 -0700
i965/fs: Rework GEN5 texturing code to use fs_reg and offset()
Now that offset() can properly handle MRF registers, we can use an MRF
fs_reg and let offset() handle incrementing it correctly for different
dispatch widths. While this doesn't have any noticeable effect currently,
it does ensure that the destination register is 16-wide which will be
necessary later when we start detecting execution sizes based on source and
destination registers.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7210583eb84a5d49803dbe37b0960373b4224d10
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Mon Aug 18 14:27:55 2014 -0700
i965/fs_reg: Allocate double the number of vgrfs in SIMD16 mode
This is actually the squash of a bunch of different changes. Individual
commit titles follow:
i965/fs: Always 2-align registers SIMD16 for gen <= 5
i965/fs: Use the register width when applying offsets
This reworks both byte_offset() and offset() to be more intelligent.
The byte_offset() function now supports offsets bigger than 32. The
offset() function uses the byte_offset() function together with the
register width and the type size to offset the register by the correct
amount.
i965/fs: Change regs_read to be in hardware registers
i965/fs: Change regs_written to be actual hardware registers
i965/fs: Properly handle register widths in LOAD_PAYLOAD
The LOAD_PAYLOAD instruction is a bit special because it collects a
bunch of registers (with possibly different widths) into a single
payload block. Once the payload is constructed, it's treated as a
single block of data and most of the information such as register widths
doesn't matter anymore. In particular, the offset of any particular
source register is the accumulation of the sizes of the previous source
registers.
i965/fs: Properly set writemasks in LOAD_PAYLOAD
i965/fs: Handle register widths in demote_pull_constants
i965/fs: Get rid of implicit register doubling in the allocator
i965/fs: Reserve enough registers for PLN instructions
i965/fs: Make sources and destinations interfere in 16-wide
i965/fs: Properly handle register widths in CSE
i965/fs: Properly handle register widths in register_coalesce
i965/fs: Properly handle widths in copy propagation
i965/fs: Properly handle register widths in VARYING_PULL_CONSTANT_LOAD
i965/fs: Properly handle register widths and odd register sizes in spilling
i965/fs: Don't waste a register on texture lookups for gen >= 7
Previously, we were waisting a register in SIMD16 mode because we could
only allocate registers in pairs. Now that we can allocate and address
odd-sized registers, let's get rid of this special-case.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4232a776a699d80601496802ab2d817374a31f56
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Aug 13 14:42:40 2014 -0700
i965/fs: Handle printing of registers better.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5390ca8ce93028d2d6016d4817e92427d09e4a21
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Sep 25 12:06:42 2014 -0700
i965: Explicitly set widths on gen5 math instruction destinations.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=004fbd53759a8993198883a32d93c9e3f6a65bbd
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Sat Aug 16 10:48:18 2014 -0700
i965/fs: Make half() divide the register width by 2 and use it more
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24d023b9fe18847158ec6c14e1e0e32ff022f060
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Aug 13 12:25:58 2014 -0700
i965/fs: Add a concept of a width to fs_reg
Every register in i965 assembly implicitly has a concept of a "width".
Usually, this is derived from the execution size of the instruction.
However, when writing a compiler it turns out that it is frequently a
useful to have the width explicitly in the register and derive the
execution size of the instruction from the widths of the registers used in
it.
This commit adds a width field to fs_reg along with an effective_width()
helper function. The effective_width() function tells you how wide the
register effectively is when used in an instruction. For example, uniform
values have width 1 since the data is not actually repeated, but when used
in an instruction they take on the width of the instruction. However, for
some instructions (LOAD_PAYLOAD being the notable exception), the width is
not the same.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1030ee6e9b0cc6c05a7f25c17c0cf722a6731c89
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Sep 19 16:42:10 2014 -0700
i965/fs: A little harmless refactoring of register_coalesce
Just pass the visitor into is_copy_payload() and is_coalesce_candidate()
instead of a register size and the virtual_grf_sizes array. Among other
things, this makes the code more obvious because you don't have to figure
out where src_size came from.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f91b566f55390d1a0e472ac970d017374b91ee83
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Aug 13 12:23:47 2014 -0700
i965/brw_reg: Add a firsthalf function and use it in the generator
Right now, this function is a no-op but it indicates that we intend to only
use the first half of the 16-wide register.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1728e74957a62b1b4b9fbb62a7de2c12b77c8a75
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Sep 23 17:22:09 2014 -0700
i965/fs: Copy propagate partial reads.
This commit reworks copy propagation a bit to support propagating the
copying of partial registers. This comes up every time we have pull
constants because we do a pull constant read immediately followed by a move
to splat the one component of the out to 8 or 16-wide. This allows us to
eliminate the copy and simply use the one component of the register.
Shader DB results:
total instructions in shared programs: 5044937 -> 5044428 (-0.01%)
instructions in affected programs: 66112 -> 65603 (-0.77%)
GAINED: 0
LOST: 0
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d5f0eb0487ad13e90f7248c95c023c35457eaf9
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Sat Sep 13 11:49:55 2014 -0700
i965/fs: Refactor fs_inst::is_send_from_grf()
A switch statement is much easier to read/edit than a big giant or
statement.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54688cd03b087740173b0e11638df1cf0f3a19e1
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Sep 12 17:49:49 2014 -0700
i965/fs: Clean up emit_fb_writes
This splits emit_fb_writes into two functions: emit_fb_writes and
emit_single_fb_write. This reduces the amount of duplicated code in
emit_fb_writes and makes the register number fiddling less arcane.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=72a3780f26951c405c35a1ae51598f7b0a65b92f
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Sep 16 15:56:47 2014 -0700
i965/fs: Print BAD_FILE registers in dump_instruction
Sometimes these show up in LOAD_PAYLOAD instructions and it's nice to be
able to see them.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2af4b0aeaff53190b0e17a971119d1b77ddad25b
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Sep 16 13:14:09 2014 -0700
i965/fs: Make compact_virtual_grfs an optimization pass
Previously we disabled compact_virtual_grfs when dumping optimizations.
The idea here was to make it easier to diff the dumped shader because you
didn't have a sudden renaming. However, sometimes a bug is affected by
compact_virtual_grfs and, when this happens, you want to keep dumping
instructions with compact_virtual_grfs enabled. By turning it into an
optimization pass and dumping it along with the others, we retain the
ability to diff because you can just diff against the compact_virtual_grf
output.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a25db10c1248d70cf7f4097833fa03fdccd98fe8
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Sep 10 10:17:28 2014 -0700
i964/fs: Make immediate fs_reg constructors explicit
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c89e098e8e644d6c33b36fabbba0b8d675d115d
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Sep 10 11:28:27 2014 -0700
i965/fs: Make null_reg_* const members of fs_visitor instead of globals
We also set the register width equal to the dispatch width. Right now,
this is effectively a no-op since we don't do anything with it. However,
it will be important once we add an actual width field to fs_reg.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab7234c8520499fcfeed153e0aefeb6b43758d1f
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Mon Sep 8 18:34:28 2014 -0700
i965/fs: Use the var_from_vgrf helper function instead of doing it manually
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c24dd54f973d1a42b0e2cc81aa219bb58f7523d9
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Sep 24 13:16:43 2014 -0700
i965/fs: Fix a bug with dead_code_eliminate on large writes
Previously, if an instruction wrote to more than one register, we
implicitly assumed that it filled the entire register. We never hit this
before because the only time we did multi-register writes was things like
texturing which always wrote to all of the registers. However, with the
upcoming ability to do 16-wide instructions in SIMD8 and things of that
nature, we can have multi-register writes at offsets and we'll hit this.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1385a4b706afa71eebcb72cd232faecc0b956b50
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Mon Sep 8 15:26:24 2014 -0700
i965/fs: Use the UW type for the destination of VARYING_PULL_CONSTANT_LOAD
instructions
Using a floating-point type doesn't usually cause hangs on my HSW, but the
simulator complains about it quite a bit.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0d43c09b2fa32db66b7b6dc13becb0c7d3edeea
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Sat Sep 6 13:48:34 2014 -0700
i965/fs: Use offset a lot more places
We have this wonderful offset() function for advancing registers, but we're
not using it. Using offset() allows us to do some sanity checking and
avoid manually touching fs_reg::reg_offset. In a few commits, we will make
offset do even more nifty things for us.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0089d025aa7f7497b3097c5067b589410cd40fbc
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Aug 19 16:11:36 2014 -0700
i965/fs: fix a comment in compact_virtual_grfs
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3dc3fccb7586e6198c50114d6245017fc9badde8
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Aug 19 13:57:11 2014 -0700
i965/fs: Rewrite fs_visitor::split_virtual_grfs
The original vgrf splitting code was written with the assumption that vgrfs
came in two types: those that can be split into single registers and those
that can't be split at all It was very conservative and bailed as soon as
more than one element of a register was read or written. This won't work
once we start allowing a regular MOV or ADD operation to operate on
multiple registers. This rewrite allows for the case where a vgrf of size
5 may appropriately be split in to one register of size 1 and two registers
of size 2.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Acked-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9da0740e22f27a6f8bd429f0bb768752b311398
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Sat Sep 6 10:37:22 2014 -0700
i965/fs_live_variables: Use var_from_vgrf insead of repeating the
calculation
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75afe17b7954984ea5b55c2a6d5d124f5eb03328
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Sep 26 14:47:03 2014 -0700
i965/fs: Manually generate the meta fast-clear shader
Previously, we were generating the fast-clear shader from GLSL. The
problem is that fast clears require that we use a replicated write rather
than a regular write instruction. In order to get this we had a
complicated and somewhat fragile optimization pass that looked for places
where we can use a replicated write and used it. Since replicated writes
have a lot of restrictions, we only ever use them for fast-clear
operations.
This commit replaces the optimization pass with a function that just
generates the shader we want. This is a) less code, b) less fragile than
the optimization pass, and c) generates a more efficient shader.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Kristian Høgsberg <k...@bitplanet.net>
Acked-by: Kenneth Graunke <kenn...@whitecape.org>
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