Module: Mesa Branch: master Commit: 822e791321c387cadcec562820a0521aae90cc77 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=822e791321c387cadcec562820a0521aae90cc77
Author: Kenneth Graunke <[email protected]> Date: Mon Apr 21 16:37:04 2014 -0700 i965/skl: Set mask bits in PIPELINE_SELECT on Skylake. Skylake has some extra bits in PIPELINE_SELECT, none of which are interesting for a 3D driver. In order to selectively change them, it also introduces new "mask bits" in 15:8. We care about the "Pipeline Selection" bits (1:0), so set the mask to 0x3. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> --- src/mesa/drivers/dri/i965/brw_misc_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index e3980fc..99fcddc 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -902,7 +902,7 @@ brw_upload_invariant_state(struct brw_context *brw) const uint32_t _3DSTATE_PIPELINE_SELECT = is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45; BEGIN_BATCH(1); - OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | 0); + OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | (brw->gen >= 9 ? (3 << 8) : 0)); ADVANCE_BATCH(); if (brw->gen < 6) { _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
