URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1829f9c928836940fa13b12a8b073f09c26dc782
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 17:08:57 2015 +0100

    radeonsi: enable LLVM optimizations that assume no NaNs for non-compute 
shaders
    
    v2: complete rewrite
    
    Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
    Reviewed-by: Tom Stellard <thomas.stell...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8185aa9a8e3588fe014faef8afaeae56d45e90b
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Tue Dec 30 18:41:25 2014 +0100

    radeonsi: emit SURFACE_SYNC last
    
    This fixes a case where a transform feedback buffer is fed back as an index
    buffer, because SURFACE_SYNC must be after VS_PARTIAL_FLUSH.
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c9ec6ca7ee30109f0bcf0f3f4bcee6fb30dac81
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Mon Dec 29 15:09:22 2014 +0100

    radeonsi: flush all CB/DB caches unconditionally when changing the 
framebuffer
    
    This is easier to read and will work better with shader image stores.
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1bbccf5214f95d8e23d6da88f51aae6032cbfe9
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Mon Dec 29 01:25:48 2014 +0100

    radeonsi: change TC cache flushing strategy for textures
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca9c5b2be5ed6aa34032264432bb5465d37641ed
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Tue Dec 30 16:45:51 2014 +0100

    radeonsi: improve and fix streamout flushing
    
    - we don't usually need to flush TC L2
    - we should flush KCACHE
      (not really an issue now since we always flush KCACHE when updating
       descriptors, but it could be a problem if we used CE, which doesn't
       require flushing KCACHE)
    - add an explicit VS_PARTIAL_FLUSH flag
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=18a30c97780bef9c498db915ba5e7debe832f576
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Mon Dec 29 14:53:11 2014 +0100

    radeonsi: use TC L2 for CP DMA operations with shader resources on CIK
    
    So that TC L2 doesn't need to be flushed.
    
    The only problem is with index buffers, which don't use TC.
    A simple solution is added that flushes TC L2 before a draw call 
(TC_L2_dirty).
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11b76369f53e064bef1bad629f957373c0e93b6c
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Mon Dec 29 13:22:00 2014 +0100

    radeonsi: use TC L2 for updating descriptors on CIK
    
    This allows not flushing TC L2 on CIK later.
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=02ba7334d35cf8182048c17a149b16f18104c6bf
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 22:16:53 2015 +0100

    radeonsi: don't use TC L2 for updating descriptors on SI
    
    It's causing problems, because we mix uncached CP DMA with cached WRITE_DATA
    when updating the same memory.
    
    The solution for SI is to use uncached access here, because CP DMA doesn't
    support cached access.
    
    CIK will be handled in the next patch.
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=edf18da85dd3b1865c4faaba650a8fa371b7103c
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Mon Dec 29 14:45:49 2014 +0100

    radeonsi: only flush the right set of caches for CP DMA operations
    
    That's either framebuffer caches or caches for shader resources.
    The motivation is that framebuffer caches need to be flushed very rarely
    here.
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73c2b0d18c51459697d8ec194ecfc4438c98c139
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Dec 28 23:11:38 2014 +0100

    radeonsi: implement separate ICACHE and KCACHE flush for SI
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0aecf9e2d18804d83473a5cc142297c1bbae04f8
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Tue Dec 30 13:08:32 2014 +0100

    radeonsi: add a combined flag for flushing a framebuffer
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2bfe9d4538693ebad3c0330a92e432c6c4c5afd3
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Mon Dec 29 14:02:46 2014 +0100

    radeonsi: rename flush flags, split the TC flag into L1 and L2
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d217819e7872e1017260f525caff38e6e49e714d
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Mon Dec 29 13:39:42 2014 +0100

    r600g,radeonsi: separate cache flush flags
    
    I will rename them for radeonsi.
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d14f2ab4ad34536d46d0033117a859c53db0c976
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Mon Dec 29 13:27:46 2014 +0100

    r600g: move r6xx-specific streamout flush flagging into r600g
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0543630d0b0d9d9f6eefbc14fbd3385d4de37ba0
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 22:01:43 2015 +0100

    radeonsi: only set BC_OPTIMIZE_DISABLE when necessary
    
    SPI_PS_IN_CONTROL is moved into the SPI mapping state.
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d8e838dae0f2c94f8e5129c08aaa80eb6aabc81
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 21:05:14 2015 +0100

    radeonsi: do not define FACE as an ordinary PS input
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15a7fff69a644856945f461e4b2c62c3a13872fb
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 20:23:51 2015 +0100

    radeonsi: remove flatshade from the shader key
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=13de9475fc237dd000bb0ef1d7784b86bee54b39
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 20:09:51 2015 +0100

    radeonsi: remove special handling of TGSI_INTERPOLATE_COLOR in shader 
codegen
    
    It doesn't do anything useful. And colors are floating-point, so we can use
    fs.interp, remove "flatshade" from the shader key, and rely on the 
FLAT_SHADE
    state only (in the next patch).
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3d4bdd6a854591a54733b7b68035f1a30baeafe
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 14:51:01 2015 +0100

    radeonsi: implement VERTEXID_NOBASE and BASEVERTEX system values
    
    Only done for completeness. Not used by anything yet.
    
    Tested by advertising PIPE_CAP_VERTEXID_NOBASE.
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7c6f397f44ae6a0ba63d8734b133196fe88443e
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 14:41:49 2015 +0100

    radeonsi: fix VertexID for OpenGL
    
    This fixes all failing piglit VertexID tests.
    
    Cc: 10.4 <mesa-sta...@lists.freedesktop.org>
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=368b0a734045db0c8d3b44a00c6499bfb70c6411
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Dec 28 21:51:35 2014 +0100

    radeonsi: clarify a hw bug in shader exports
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1d2af2398fc439865f08f1008cb03675da80264
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 20:45:35 2015 +0100

    radeonsi: use ordered compares for SSG and face selection
    
    Ordered compares are what you have in C. Unordered compares are the result
    of negating ordered compares (they return true if either argument is NaN).
    
    That special NaN behavior is completely useless here, and unordered
    compares produce horrible code with all stable LLVM versions.
    (I think that has been fixed in LLVM git)
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a38e8de643fac4990d666cea3da895f9120b9e28
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Wed Dec 31 00:51:27 2014 +0100

    radeonsi: remove unused and not useful variables
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=638fa8016a39db95361922ea63390f34654aef37
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Wed Dec 31 00:42:22 2014 +0100

    radeonsi: remove init config from states
    
    It really doesn't do anything there.
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9141d8855555e45a057970e78969e1518ad3617d
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Tue Dec 30 23:49:59 2014 +0100

    radeonsi: reduce the size of si_pm4_state
    
    - the relocs array is unused, remove it
    - ndw is at most 115 (init), set 140 as the maximum
    - compute needs 4 buffers per state, graphics only needs 1; set 4 as the 
maximum
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b82eb677de63ec49f56800b81ac49b79fc5576a
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 21:58:42 2015 +0100

    tgsi: add uses_centroid into tgsi_shader_info

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eaae92a349af1fd6641c4bdd4bfd1185b1b6fe3e
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 15:43:47 2015 +0100

    st/mesa: fix GL_PRIMITIVE_RESTART_FIXED_INDEX
    
    Cc: 10.2 10.3 10.4 <mesa-sta...@lists.freedesktop.org>
    Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f5d3095211eee609dfd52eee9f64ce8492b956b
Author: Marek Olšák <marek.ol...@amd.com>
Date:   Sun Jan 4 14:27:33 2015 +0100

    vbo: ignore primitive restart if FixedIndex is enabled in DrawArrays
    
    From GL 4.4 Core profile:
    
      If both PRIMITIVE_RESTART and PRIMITIVE_RESTART_FIXED_INDEX are
      enabled, the index value determined by PRIMITIVE_RESTART_FIXED_INDEX is
      used. If PRIMITIVE_RESTART_FIXED_INDEX is enabled, primitive restart is 
not
      performed for array elements transferred by any drawing command not 
taking a
      type parameter, including all of the *Draw* commands other than *DrawEle-
      ments*.
    
    Cc: 10.2 10.3 10.4 <mesa-sta...@lists.freedesktop.org>
    Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

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