Module: Mesa
Branch: vulkan
Commit: 75af420cb1145f5fc34af6728047a2404b5f1add
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75af420cb1145f5fc34af6728047a2404b5f1add

Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date:   Mon Mar  7 18:07:48 2016 -0800

anv/pipeline: Move binding table setup to its own helper

---

 src/intel/vulkan/anv_pipeline.c | 39 ++++++++++++++++++---------------------
 1 file changed, 18 insertions(+), 21 deletions(-)

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 86831ea..22af44d 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -366,27 +366,6 @@ anv_pipeline_compile(struct anv_pipeline *pipeline,
    if (pipeline->layout)
       anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
 
-   /* All binding table offsets provided by apply_pipeline_layout() are
-    * relative to the start of the bindint table (plus MAX_RTS for VS).
-    */
-   unsigned bias;
-   switch (stage) {
-   case MESA_SHADER_FRAGMENT:
-      bias = MAX_RTS;
-      break;
-   case MESA_SHADER_COMPUTE:
-      bias = 1;
-      break;
-   default:
-      bias = 0;
-      break;
-   }
-   prog_data->binding_table.size_bytes = 0;
-   prog_data->binding_table.texture_start = bias;
-   prog_data->binding_table.ubo_start = bias;
-   prog_data->binding_table.ssbo_start = bias;
-   prog_data->binding_table.image_start = bias;
-
    /* Finish the optimization and compilation process */
    if (nir->stage == MESA_SHADER_COMPUTE)
       brw_nir_lower_shared(nir);
@@ -400,6 +379,16 @@ anv_pipeline_compile(struct anv_pipeline *pipeline,
 }
 
 static void
+anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
+{
+   prog_data->binding_table.size_bytes = 0;
+   prog_data->binding_table.texture_start = bias;
+   prog_data->binding_table.ubo_start = bias;
+   prog_data->binding_table.ssbo_start = bias;
+   prog_data->binding_table.image_start = bias;
+}
+
+static void
 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
                                 gl_shader_stage stage,
                                 const struct brw_stage_prog_data *prog_data,
@@ -463,6 +452,8 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
       if (nir == NULL)
          return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
+      anv_fill_binding_table(&prog_data.base.base, 0);
+
       void *mem_ctx = ralloc_context(NULL);
 
       if (module->nir == NULL)
@@ -549,6 +540,8 @@ anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
       if (nir == NULL)
          return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
+      anv_fill_binding_table(&prog_data.base.base, 0);
+
       void *mem_ctx = ralloc_context(NULL);
 
       if (module->nir == NULL)
@@ -643,6 +636,8 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
          }
       }
 
+      anv_fill_binding_table(&prog_data.base, MAX_RTS);
+
       void *mem_ctx = ralloc_context(NULL);
 
       if (module->nir == NULL)
@@ -740,6 +735,8 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
       if (nir == NULL)
          return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
+      anv_fill_binding_table(&prog_data.base, 1);
+
       prog_data.base.total_shared = nir->num_shared;
 
       void *mem_ctx = ralloc_context(NULL);

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