Module: Mesa
Branch: master
Commit: f6704f2a4db7113e597d4bab2cefc02e166c2ad9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6704f2a4db7113e597d4bab2cefc02e166c2ad9
Author: Axel Davy <axel.d...@ens.fr>
Date: Tue Jun 14 23:13:26 2016 +0200
r600g: Implement POLYGON_OFFSET_UNITS_UNSCALED
Empirical tests show that the polygon offset
behaviour is entirely determined by the content of
the PA_SU_POLY_OFFSET states, and not by the depth buffer
format bound.
PA_SU_POLY_OFFSET seems to directly set the parameters of
the polygon offset formula, and setting 0 for
PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth
bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled
behaviour.
Signed-off-by: Axel Davy <axel.d...@ens.fr>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/r600/evergreen_state.c | 39 +++++++++++++++-------------
src/gallium/drivers/r600/r600_pipe.c | 2 +-
src/gallium/drivers/r600/r600_pipe.h | 2 ++
src/gallium/drivers/r600/r600_state.c | 35 +++++++++++++------------
src/gallium/drivers/r600/r600_state_common.c | 4 ++-
5 files changed, 46 insertions(+), 36 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 797f593..fab0359 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -492,6 +492,7 @@ static void *evergreen_create_rs_state(struct pipe_context
*ctx,
rs->offset_units = state->offset_units;
rs->offset_scale = state->offset_scale * 16.0f;
rs->offset_enable = state->offset_point || state->offset_line ||
state->offset_tri;
+ rs->offset_units_unscaled = state->offset_units_unscaled;
if (state->point_size_per_vertex) {
psize_min = util_get_min_point_size(state);
@@ -1665,24 +1666,26 @@ static void evergreen_emit_polygon_offset(struct
r600_context *rctx, struct r600
float offset_scale = state->offset_scale;
uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
- switch (state->zs_format) {
- case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- case PIPE_FORMAT_X8Z24_UNORM:
- case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- offset_units *= 2.0f;
- pa_su_poly_offset_db_fmt_cntl =
- S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
- break;
- case PIPE_FORMAT_Z16_UNORM:
- offset_units *= 4.0f;
- pa_su_poly_offset_db_fmt_cntl =
- S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
- break;
- default:
- pa_su_poly_offset_db_fmt_cntl =
- S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
- S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+ if (!state->offset_units_unscaled) {
+ switch (state->zs_format) {
+ case PIPE_FORMAT_Z24X8_UNORM:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ case PIPE_FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+ offset_units *= 2.0f;
+ pa_su_poly_offset_db_fmt_cntl =
+ S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
+ break;
+ case PIPE_FORMAT_Z16_UNORM:
+ offset_units *= 4.0f;
+ pa_su_poly_offset_db_fmt_cntl =
+ S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
+ break;
+ default:
+ pa_su_poly_offset_db_fmt_cntl =
+ S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23)
|
+ S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+ }
}
radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
4);
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index fe1af7c..57721d9 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -282,6 +282,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
case PIPE_CAP_QUERY_MEMORY_INFO:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+ case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
return 1;
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
@@ -370,7 +371,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_TGSI_VOTE:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
- case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
return 0;
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 9677bb6..0dd538b 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -273,6 +273,7 @@ struct r600_rasterizer_state {
float offset_units;
float offset_scale;
bool offset_enable;
+ bool offset_units_unscaled;
bool scissor_enable;
bool multisample_enable;
};
@@ -282,6 +283,7 @@ struct r600_poly_offset_state {
enum pipe_format zs_format;
float offset_units;
float offset_scale;
+ bool offset_units_unscaled;
};
struct r600_blend_state {
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 578aef9..89a9f25 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -256,22 +256,24 @@ static void r600_emit_polygon_offset(struct r600_context
*rctx, struct r600_atom
float offset_scale = state->offset_scale;
uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
- switch (state->zs_format) {
- case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- offset_units *= 2.0f;
- pa_su_poly_offset_db_fmt_cntl =
- S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
- break;
- case PIPE_FORMAT_Z16_UNORM:
- offset_units *= 4.0f;
- pa_su_poly_offset_db_fmt_cntl =
- S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
- break;
- default:
- pa_su_poly_offset_db_fmt_cntl =
- S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
- S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+ if (!state->offset_units_unscaled) {
+ switch (state->zs_format) {
+ case PIPE_FORMAT_Z24X8_UNORM:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ offset_units *= 2.0f;
+ pa_su_poly_offset_db_fmt_cntl =
+ S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
+ break;
+ case PIPE_FORMAT_Z16_UNORM:
+ offset_units *= 4.0f;
+ pa_su_poly_offset_db_fmt_cntl =
+ S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
+ break;
+ default:
+ pa_su_poly_offset_db_fmt_cntl =
+ S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23)
|
+ S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+ }
}
radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
4);
@@ -492,6 +494,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
rs->offset_units = state->offset_units;
rs->offset_scale = state->offset_scale * 16.0f;
rs->offset_enable = state->offset_point || state->offset_line ||
state->offset_tri;
+ rs->offset_units_unscaled = state->offset_units_unscaled;
if (state->point_size_per_vertex) {
psize_min = util_get_min_point_size(state);
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 1ca583c..ce644b7 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -350,9 +350,11 @@ static void r600_bind_rs_state(struct pipe_context *ctx,
void *state)
if (rs->offset_enable &&
(rs->offset_units != rctx->poly_offset_state.offset_units ||
- rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
+ rs->offset_scale != rctx->poly_offset_state.offset_scale ||
+ rs->offset_units_unscaled !=
rctx->poly_offset_state.offset_units_unscaled)) {
rctx->poly_offset_state.offset_units = rs->offset_units;
rctx->poly_offset_state.offset_scale = rs->offset_scale;
+ rctx->poly_offset_state.offset_units_unscaled =
rs->offset_units_unscaled;
r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
}
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