Module: Mesa
Branch: master
Commit: 74e39de9324d2d2333cda6adca50ae2a3fc36de2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74e39de9324d2d2333cda6adca50ae2a3fc36de2
Author: Marek Olšák <marek.ol...@amd.com>
Date: Fri Oct 28 23:08:50 2016 +0200
radeonsi: set IF_THRESHOLD to 3
Piglit regressions (radeonsi or LLVM bugs, they pass on softpipe):
- glsl-1.10/execution/variable-indexing/vs-output-array-vec3-index-wr
- glsl-1.10/execution/variable-indexing/vs-output-array-vec4-index-wr
- glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-col-row-wr
- glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-row-wr
Totals:
SGPRS: 1132185 -> 1168801 (3.23 %)
VGPRS: 907856 -> 906204 (-0.18 %)
Spilled SGPRs: 2011 -> 2425 (20.59 %)
Spilled VGPRs: 368 -> 96 (-73.91 %)
Scratch VGPRs: 1344 -> 1060 (-21.13 %) dwords per thread
Code Size: 35916164 -> 35705372 (-0.59 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 194010 -> 194921 (0.47 %)
Wait states: 0 -> 0 (0.00 %)
Before:
VGPR SPILLING APPS Shaders SpillVGPR ScratchVGPR
alien_isolation 2938 38 40
bioshock-infinite 1769 245 732
dirt-showdown 548 85 72
f1-2015 776 0 320
ue4_lightroom_inter.. 74 0 180
After:
VGPR SPILLING APPS Shaders SpillVGPR ScratchVGPR
alien_isolation 2938 38 40
bioshock-infinite 1769 0 480
dirt-showdown 548 58 40
f1-2015 776 0 320
ue4_lightroom_inter.. 74 0 180
Bioshock and DiRT benefit.
If I set IF_THRESHOLD=4, tesseract starts spilling VGPRs
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
src/gallium/drivers/radeonsi/si_pipe.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 146128d..6be676d 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -632,6 +632,8 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
unsigned shader, enu
return 32;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
+ case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
+ return 3;
/* Supported boolean features. */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
@@ -659,7 +661,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
unsigned shader, enu
case PIPE_SHADER_CAP_SUPPORTED_IRS:
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
- case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
return 0;
}
return 0;
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