Module: Mesa
Branch: master
Commit: 591e14ec08b13e8d50636feb1afa578257175b9d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=591e14ec08b13e8d50636feb1afa578257175b9d
Author: Francisco Jerez <curroje...@riseup.net>
Date: Thu Dec 8 18:00:17 2016 -0800
i965/gen6+: Invalidate constant cache on brw_emit_mi_flush().
In order to make sure that the constant cache is coherent with
previous rendering when we start using it for pull constant loads.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index dd426bf..b8f7406 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -351,6 +351,7 @@ brw_emit_mi_flush(struct brw_context *brw)
int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
if (brw->gen >= 6) {
flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
+ PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_VF_CACHE_INVALIDATE |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
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