Module: Mesa
Branch: master
Commit: 0232ea8025d3da65295c0af1b8f4ca8fc97a74dd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0232ea8025d3da65295c0af1b8f4ca8fc97a74dd
Author: Dave Airlie <airl...@redhat.com>
Date: Tue Mar 28 11:48:38 2017 +1000
radv: move pa_cl_vs_out_cntl calculation to pipeline
This also takes the side band setting code from radeonsi.
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/amd/vulkan/radv_cmd_buffer.c | 16 +---------------
src/amd/vulkan/radv_pipeline.c | 31 ++++++++++++++++++++++++++++++-
src/amd/vulkan/radv_private.h | 2 +-
3 files changed, 32 insertions(+), 17 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 92e68efa86..04c28d6a29 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -540,23 +540,9 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
S_028818_VPORT_Y_SCALE_ENA(1) |
S_028818_VPORT_Y_OFFSET_ENA(1) |
S_028818_VPORT_Z_SCALE_ENA(1) |
S_028818_VPORT_Z_OFFSET_ENA(1));
- unsigned clip_dist_mask, cull_dist_mask, total_mask;
- clip_dist_mask = outinfo->clip_dist_mask;
- cull_dist_mask = outinfo->cull_dist_mask;
- total_mask = clip_dist_mask | cull_dist_mask;
radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
-
S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
-
S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
-
S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
-
S_02881C_VS_OUT_MISC_VEC_ENA(outinfo->writes_pointsize ||
-
outinfo->writes_layer ||
-
outinfo->writes_viewport_index) |
- S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask &
0x0f) != 0) |
- S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask &
0xf0) != 0) |
- pipeline->graphics.raster.pa_cl_vs_out_cntl |
- cull_dist_mask << 8 |
- clip_dist_mask);
+ pipeline->graphics.pa_cl_vs_out_cntl);
radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index c7d74805a2..252808d7a7 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1126,7 +1126,7 @@ radv_pipeline_init_raster_state(struct radv_pipeline
*pipeline,
S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0
at bottom
- raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
+
raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0)
|
@@ -1527,6 +1527,33 @@ static uint32_t si_vgt_gs_mode(struct
radv_shader_variant *gs)
S_028A40_GS_WRITE_OPTIMIZE(1);
}
+static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
+{
+ struct radv_shader_variant *vs;
+ vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader :
pipeline->shaders[MESA_SHADER_VERTEX];
+
+ struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
+
+ unsigned clip_dist_mask, cull_dist_mask, total_mask;
+ clip_dist_mask = outinfo->clip_dist_mask;
+ cull_dist_mask = outinfo->cull_dist_mask;
+ total_mask = clip_dist_mask | cull_dist_mask;
+
+ bool misc_vec_ena = outinfo->writes_pointsize ||
+ outinfo->writes_layer ||
+ outinfo->writes_viewport_index;
+ pipeline->graphics.pa_cl_vs_out_cntl =
+ S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
+ S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
+ S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
+ S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
+ S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
+ S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
+ S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
+ cull_dist_mask << 8 |
+ clip_dist_mask;
+
+}
static void calculate_ps_inputs(struct radv_pipeline *pipeline)
{
struct radv_shader_variant *ps, *vs;
@@ -1742,7 +1769,9 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
V_028710_SPI_SHADER_ZERO;
+ calculate_pa_cl_vs_out_cntl(pipeline);
calculate_ps_inputs(pipeline);
+
const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState;
for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++)
{
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index bf3d19ce9e..0b8c86df79 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -905,7 +905,6 @@ unsigned radv_format_meta_fs_key(VkFormat format);
struct radv_raster_state {
uint32_t pa_cl_clip_cntl;
- uint32_t pa_cl_vs_out_cntl;
uint32_t spi_interp_control;
uint32_t pa_su_point_size;
uint32_t pa_su_point_minmax;
@@ -965,6 +964,7 @@ struct radv_pipeline {
unsigned gsvs_ring_size;
uint32_t ps_input_cntl[32];
uint32_t ps_input_cntl_num;
+ uint32_t pa_cl_vs_out_cntl;
struct radv_prim_vertex_count prim_vertex_count;
} graphics;
};
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