Module: Mesa
Branch: master
Commit: a8fde221a8f9a561c592a7d51a656d10037c7912
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8fde221a8f9a561c592a7d51a656d10037c7912
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Tue May 23 21:03:14 2017 -0700
i965: Set the "Float Blend Optimization Enable" bit on Gen9+.
This is woefully undocumented. It's some kind of optimization that
avoids unnecessary render target reads when blending with a floating
point render target, using independent alpha blending modes.
The internal documentation indicates that this bit exists on Cherryview
as well, but the other driver doesn't appear to set it on that platform.
There's also some confusing wording that indicates that it may exist on
Broadwell, but the documentation says it's reserved, so who knows.
I was not able to find any workload that benefited from setting this
bit, but it seems like a good idea to set it nonetheless.
Reviewed-by: Plamena Manolova <plamena.manol...@intel.com>
Acked-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index ace83ef57a..312dddafd7 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1609,6 +1609,7 @@ enum brw_pixel_shader_coverage_mask_mode {
#define GEN7_GPGPU_DISPATCHDIMZ 0x2508
#define GEN7_CACHE_MODE_1 0x7004
+# define GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
# define GEN8_HIZ_NP_PMA_FIX_ENABLE (1 << 11)
# define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13)
# define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index bcb7ff1231..4647f1c41e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -65,7 +65,9 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(GEN7_CACHE_MODE_1);
- OUT_BATCH(REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
+ OUT_BATCH(REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
+ REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
+ GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
ADVANCE_BATCH();
}
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