Module: Mesa
Branch: master
Commit: 5589ba983d13897afa0cd15b6010d094ac1e2908
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5589ba983d13897afa0cd15b6010d094ac1e2908
Author: Rob Clark <robdcl...@gmail.com>
Date: Sat Jun 3 12:42:35 2017 -0400
freedreno/a5xx: refactor out helper for LRZ flush
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
src/gallium/drivers/freedreno/a5xx/fd5_emit.c | 3 ---
src/gallium/drivers/freedreno/a5xx/fd5_emit.h | 15 +++++++++++++++
src/gallium/drivers/freedreno/a5xx/fd5_gmem.c | 12 ++++--------
3 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index 73684c9f90..2c31831c97 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -795,9 +795,6 @@ t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
OUT_RING(ring, 0x00000012);
- OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
- OUT_RING(ring, 0x00000000);
-
OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.h
b/src/gallium/drivers/freedreno/a5xx/fd5_emit.h
index ca88083068..7df7eb7123 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.h
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.h
@@ -160,7 +160,22 @@ fd5_emit_render_cntl(struct fd_context *ctx, bool blit,
bool binning)
OUT_RING(ring, 0x00000008 | /* GRAS_SC_CNTL */
COND(binning, A5XX_GRAS_SC_CNTL_BINNING_PASS) |
COND(samples_passed, A5XX_GRAS_SC_CNTL_SAMPLES_PASSED));
+}
+
+static inline void
+fd5_emit_lrz_flush(struct fd_ringbuffer *ring)
+{
+ /* TODO I think the extra writes to GRAS_LRZ_CNTL are probably
+ * a workaround and not needed on all a5xx.
+ */
+ OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
+ OUT_RING(ring, A5XX_GRAS_LRZ_CNTL_ENABLE);
+
+ OUT_PKT7(ring, CP_EVENT_WRITE, 1);
+ OUT_RING(ring, LRZ_FLUSH);
+ OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
+ OUT_RING(ring, 0x0);
}
void fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit);
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
index b403dad5e6..6669885959 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
@@ -348,8 +348,7 @@ fd5_emit_tile_init(struct fd_batch *batch)
fd5_emit_restore(batch, ring);
- OUT_PKT7(ring, CP_EVENT_WRITE, 1);
- OUT_RING(ring, LRZ_FLUSH);
+ fd5_emit_lrz_flush(ring);
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
@@ -629,8 +628,7 @@ fd5_emit_tile_fini(struct fd_batch *batch)
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
- OUT_PKT7(ring, CP_EVENT_WRITE, 1);
- OUT_RING(ring, LRZ_FLUSH);
+ fd5_emit_lrz_flush(ring);
fd5_cache_flush(batch, ring);
fd5_set_render_mode(batch->ctx, ring, BYPASS);
@@ -644,8 +642,7 @@ fd5_emit_sysmem_prep(struct fd_batch *batch)
fd5_emit_restore(batch, ring);
- OUT_PKT7(ring, CP_EVENT_WRITE, 1);
- OUT_RING(ring, LRZ_FLUSH);
+ fd5_emit_lrz_flush(ring);
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
@@ -719,8 +716,7 @@ fd5_emit_sysmem_fini(struct fd_batch *batch)
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
- OUT_PKT7(ring, CP_EVENT_WRITE, 1);
- OUT_RING(ring, LRZ_FLUSH);
+ fd5_emit_lrz_flush(ring);
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, UNK_1D);
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