Module: Mesa
Branch: master
Commit: c17e214a6bf1da97c78fa7a6192cb1b498b773a1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c17e214a6bf1da97c78fa7a6192cb1b498b773a1
Author: Anuj Phogat <anuj.pho...@gmail.com>
Date: Tue Jun 13 11:08:48 2017 -0700
anv/cnl: Don't set FloatBlendOptimizationEnable{Mask}
This field is remove from CACHE_MODE_1 register in gen10.
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/vulkan/genX_state.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 00c4105a82..7a16ec06f7 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -55,10 +55,13 @@ genX(init_device_state)(struct anv_device *device)
#if GEN_GEN >= 9
uint32_t cache_mode_1;
anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
- .PartialResolveDisableInVC = true,
- .PartialResolveDisableInVCMask = true,
+#if GEN_GEN == 9
.FloatBlendOptimizationEnable = true,
- .FloatBlendOptimizationEnableMask = true);
+ .FloatBlendOptimizationEnableMask = true,
+#endif
+ .PartialResolveDisableInVC = true,
+ .PartialResolveDisableInVCMask = true);
+
anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
lri.RegisterOffset = GENX(CACHE_MODE_1_num);
lri.DataDWord = cache_mode_1;
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