Module: Mesa
Branch: master
Commit: 87028f863967ec88ef8b7c5722f6cbf7ac6c8db6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=87028f863967ec88ef8b7c5722f6cbf7ac6c8db6
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Tue Jul 11 21:44:12 2017 -0400
freedreno/ir3: fix load_front_face conversion
The comments are correct - we get -1 and 0. However by adding 1, we
convert this into 0,1. This mostly works for conditionals, but when
negated, this will yield the wrong result. Instead just negate the
values (as they are backwards -- -1 means back instead of front).
Fixes tests/shaders/glsl-fs-frontfacing-not.shader_test and
dEQP-GLES3.functional.shaders.builtin_variable.frontfacing on A530.
The latter also tested on A306 by Rob Clark.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
---
src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index ba1c64ee37..764aeb49f1 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -1546,14 +1546,11 @@ emit_intrinsic(struct ir3_compile *ctx,
nir_intrinsic_instr *intr)
ctx->frag_face = create_input(b, 0);
ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
}
- /* for fragface, we always get -1 or 0, but that is inverse
- * of what nir expects (where ~0 is true). Unfortunately
- * trying to widen from half to full in add.s seems to do a
- * non-sign-extending widen (resulting in something that
- * gets interpreted as float Inf??)
+ /* for fragface, we get -1 for back and 0 for front. However
this is
+ * the inverse of what nir expects (where ~0 is true).
*/
dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
- dst[0] = ir3_ADD_S(b, dst[0], 0, create_immed(b, 1), 0);
+ dst[0] = ir3_NOT_B(b, dst[0], 0);
break;
case nir_intrinsic_load_local_invocation_id:
if (!ctx->local_invocation_id) {
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