Module: Mesa
Branch: master
Commit: 2bca18be446f09285c7f5b36070f5046a5590ad9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2bca18be446f09285c7f5b36070f5046a5590ad9
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Aug 2 10:48:58 2017 -0700
i965/miptree: Delete some unused layout flags
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 ++-------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ---
2 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 13f674e362..ddd835abbf 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -302,12 +302,8 @@ unwind:
static bool
needs_separate_stencil(const struct brw_context *brw,
struct intel_mipmap_tree *mt,
- mesa_format format, uint32_t layout_flags)
+ mesa_format format)
{
-
- if (layout_flags & MIPTREE_LAYOUT_FOR_BO)
- return false;
-
if (_mesa_get_format_base_format(format) != GL_DEPTH_STENCIL)
return false;
@@ -680,7 +676,7 @@ miptree_create(struct brw_context *brw,
ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
BO_ALLOC_FOR_RENDER, 0, NULL);
- if (needs_separate_stencil(brw, mt, format, layout_flags) &&
+ if (needs_separate_stencil(brw, mt, format) &&
!make_separate_stencil_surface(brw, mt)) {
intel_miptree_release(&mt);
return NULL;
@@ -700,7 +696,6 @@ miptree_create(struct brw_context *brw,
etc_format = (format != tex_format) ? tex_format : MESA_FORMAT_NONE;
- assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);
if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD)
alloc_flags |= BO_ALLOC_FOR_RENDER;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 2179318413..534ed6c7c9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -350,10 +350,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
enum {
MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
- MIPTREE_LAYOUT_GEN6_HIZ_STENCIL = 1 << 1,
- MIPTREE_LAYOUT_FOR_BO = 1 << 2,
MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3,
- MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4,
MIPTREE_LAYOUT_TILING_Y = 1 << 5,
MIPTREE_LAYOUT_TILING_NONE = 1 << 6,
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