Module: Mesa
Branch: master
Commit: fc91cbe20ba580930bac06632e7a6d4ed39bc3ab
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc91cbe20ba580930bac06632e7a6d4ed39bc3ab
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Apr 28 07:12:24 2017 -0700
spirv: Flip the tessellation winding order
It's not SPIR-V that's backwards from GLSL, it's Vulkan that's backwards
from GL. Let's make NIR consistent with the source language and do the
flipping inside the Vulkan driver instead.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/amd/vulkan/radv_pipeline.c | 1 +
src/compiler/spirv/spirv_to_nir.c | 9 ++-------
src/intel/vulkan/genX_pipeline.c | 13 ++++++++++++-
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 91577402a2..ee2a2979aa 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -262,6 +262,7 @@ radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
if (tcs_nir == NULL)
return;
+ tes_nir->info.tess.ccw = !tes_nir->info.tess.ccw;
nir_lower_tes_patch_vertices(tes_nir,
tcs_nir->info.tess.tcs_vertices_out);
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 86536856b6..6ce9d1ada3 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -2951,17 +2951,12 @@ vtn_handle_execution_mode(struct vtn_builder *b, struct
vtn_value *entry_point,
case SpvExecutionModeVertexOrderCw:
assert(b->shader->stage == MESA_SHADER_TESS_CTRL ||
b->shader->stage == MESA_SHADER_TESS_EVAL);
- /* Vulkan's notion of CCW seems to match the hardware backends,
- * but be the opposite of OpenGL. Currently NIR follows GL semantics,
- * so we set it backwards here.
- */
- b->shader->info.tess.ccw = true;
+ b->shader->info.tess.ccw = false;
break;
case SpvExecutionModeVertexOrderCcw:
assert(b->shader->stage == MESA_SHADER_TESS_CTRL ||
b->shader->stage == MESA_SHADER_TESS_EVAL);
- /* Backwards; see above */
- b->shader->info.tess.ccw = false;
+ b->shader->info.tess.ccw = true;
break;
case SpvExecutionModePointMode:
assert(b->shader->stage == MESA_SHADER_TESS_CTRL ||
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 6dfa49b873..844c11803c 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1217,7 +1217,18 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), te) {
te.Partitioning = tes_prog_data->partitioning;
- te.OutputTopology = tes_prog_data->output_topology;
+
+ /* Vulkan has its winding order backwards from GL so TRI_CCW becomes
+ * TRI_CW and vice versa.
+ */
+ if (tes_prog_data->output_topology == OUTPUT_TRI_CCW) {
+ te.OutputTopology = OUTPUT_TRI_CW;
+ } else if (tes_prog_data->output_topology == OUTPUT_TRI_CW) {
+ te.OutputTopology = OUTPUT_TRI_CCW;
+ } else {
+ te.OutputTopology = tes_prog_data->output_topology;
+ }
+
te.TEDomain = tes_prog_data->domain;
te.TEEnable = true;
te.MaximumTessellationFactorOdd = 63.0;
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