Module: Mesa
Branch: master
Commit: 33bdbc1db47cffc9c8b79d7daee51fcdcb52837e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33bdbc1db47cffc9c8b79d7daee51fcdcb52837e
Author: Tim Rowley <timothy.o.row...@intel.com>
Date: Thu Oct 19 09:13:46 2017 -0500
gallium: add more exceptions to tgsi_util_get_inst_usage_mask
A number of double/int64 operations don't have matching
read and write usage masks, which the fallthrough case of
tgsi_util_get_inst_usage_mask assumes for componentwise
tagged instructions.
No regressions in llvmpipe piglit; fixes a large number of
swr regressions.
Reviewed-by: Roland Scheidegger <srol...@vmware.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/auxiliary/tgsi/tgsi_util.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.c
b/src/gallium/auxiliary/tgsi/tgsi_util.c
index cfce59093c..afe5690ce0 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_util.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_util.c
@@ -230,13 +230,25 @@ tgsi_util_get_inst_usage_mask(const struct
tgsi_full_instruction *inst,
read_mask = TGSI_WRITEMASK_XYZ;
break;
+ case TGSI_OPCODE_DSEQ:
+ case TGSI_OPCODE_DSNE:
+ case TGSI_OPCODE_DSLT:
+ case TGSI_OPCODE_DSGE:
case TGSI_OPCODE_DP4:
case TGSI_OPCODE_PK4B:
case TGSI_OPCODE_PK4UB:
case TGSI_OPCODE_D2F:
+ case TGSI_OPCODE_D2I:
+ case TGSI_OPCODE_D2U:
case TGSI_OPCODE_I2F:
case TGSI_OPCODE_U2F:
+ case TGSI_OPCODE_U64SEQ:
+ case TGSI_OPCODE_U64SNE:
+ case TGSI_OPCODE_U64SLT:
+ case TGSI_OPCODE_U64SGE:
case TGSI_OPCODE_U642F:
+ case TGSI_OPCODE_I64SLT:
+ case TGSI_OPCODE_I64SGE:
case TGSI_OPCODE_I642F:
read_mask = TGSI_WRITEMASK_XYZW;
break;
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