Module: Mesa
Branch: master
Commit: 48eef0c18248db948378ecf9a5f9930fa467ae9f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48eef0c18248db948378ecf9a5f9930fa467ae9f
Author: Rob Clark <robdcl...@gmail.com>
Date: Sun Dec 3 11:48:56 2017 -0500
freedreno/ir3: all mem instructions have WAR hazzard
It isn't just load instructions that have write-after-read hazzard.
Fixes stk gaussian blur compute shaders.
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
src/gallium/drivers/freedreno/ir3/ir3_legalize.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_legalize.c
b/src/gallium/drivers/freedreno/ir3/ir3_legalize.c
index 3f12b68ada..b4d5db58cc 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_legalize.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_legalize.c
@@ -211,7 +211,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct
ir3_block *block)
/* both tex/sfu appear to not always immediately consume
* their src register(s):
*/
- if (is_tex(n) || is_sfu(n) || is_load(n)) {
+ if (is_tex(n) || is_sfu(n) || is_mem(n)) {
foreach_src(reg, n) {
if (reg_gpr(reg))
regmask_set(&needs_ss_war, reg);
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