Module: Mesa
Branch: master
Commit: 61a790409e3625e8a124fe6dfac394e837f31179
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=61a790409e3625e8a124fe6dfac394e837f31179
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Tue Jan 16 02:08:02 2018 +0100
radv: Always re-emit the sample position offset user SGPR.
The user SGPR location can change between pipelines, so we need to
emit it again to the pottentially changed SGPR index.
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/vulkan/radv_cmd_buffer.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7b44f5c5c8..1143aa085f 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -604,23 +604,6 @@ radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer,
radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1,
ms->pa_sc_mode_cntl_1);
- if (old_pipeline && num_samples ==
old_pipeline->graphics.ms.num_samples &&
-
old_pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions
==
pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
- return;
-
- radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
- radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
- radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
-
- radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
ms->pa_sc_mode_cntl_0);
-
- radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
-
- /* GFX9: Flush DFSM when the AA mode changes. */
- if (cmd_buffer->device->dfsm_allowed) {
- radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
- radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) |
EVENT_INDEX(0));
- }
if
(pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
uint32_t offset;
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline,
MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
@@ -650,6 +633,23 @@ radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer,
radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
offset);
cmd_buffer->sample_positions_needed = true;
}
+
+ if (old_pipeline && num_samples ==
old_pipeline->graphics.ms.num_samples)
+ return;
+
+ radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
+ radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
+ radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
+
+ radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
ms->pa_sc_mode_cntl_0);
+
+ radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
+
+ /* GFX9: Flush DFSM when the AA mode changes. */
+ if (cmd_buffer->device->dfsm_allowed) {
+ radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) |
EVENT_INDEX(0));
+ }
}
static void
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