Module: Mesa
Branch: master
Commit: 952222ddd423bce3b6e836f3ae305cbad0622e22
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=952222ddd423bce3b6e836f3ae305cbad0622e22
Author: Dave Airlie <airl...@redhat.com>
Date: Mon Feb 19 04:55:52 2018 +0000
radv/tess: don't need to look in constant for vertices_per_patch
This just avoids passing this value via user sgprs.
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/amd/common/ac_nir_to_llvm.c | 5 ++++-
src/amd/vulkan/radv_pipeline.c | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index ec4dd098ed..351e6fa9ef 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -127,6 +127,7 @@ struct radv_shader_context {
uint32_t tcs_patch_outputs_read;
uint64_t tcs_outputs_read;
+ uint32_t tcs_vertices_per_patch;
};
static inline struct radv_shader_context *
@@ -2781,7 +2782,7 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct
radv_shader_context *ctx,
LLVMValueRef param_stride, constant16;
LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
- vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9,
6);
+ vertices_per_patch = LLVMConstInt(ctx->ac.i32,
ctx->tcs_vertices_per_patch, false);
num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
@@ -6905,11 +6906,13 @@ LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.abi.load_tess_varyings = load_tcs_varyings;
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
ctx.abi.store_tcs_outputs = store_tcs_output;
+ ctx.tcs_vertices_per_patch =
shaders[i]->info.tess.tcs_vertices_out;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode =
shaders[i]->info.tess.primitive_mode;
ctx.abi.load_tess_varyings = load_tes_input;
ctx.abi.load_tess_coord = load_tess_coord;
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
+ ctx.tcs_vertices_per_patch =
shaders[i]->info.tess.tcs_vertices_out;
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
if (shader_info->info.vs.needs_instance_id) {
if (ctx.options->key.vs.as_ls) {
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 88646fda2f..a2dec0e3bd 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1391,7 +1391,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
tess.tcs_out_offsets = (output_patch0_offset / 16) |
((perpatch_output_offset / 16) << 16);
tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16)
|
- (num_tcs_output_cp << 9) | num_patches;
+ num_patches;
tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
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