Module: Mesa
Branch: master
Commit: 56dc9f9f49638e0769d6bc696ff7f5dafccec9fc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56dc9f9f49638e0769d6bc696ff7f5dafccec9fc
Author: Anuj Phogat <anuj.pho...@gmail.com>
Date: Tue Feb 6 17:09:09 2018 -0800
intel/compiler: Memory fence commit must always be enabled for gen10+
Commit bit in the message descriptor (Bit 13) must be always set
to true in CNL+ for memory fence messages. It also fixes a piglit
GPU hang on cnl+ in simulation environment.
Piglit test: arb_shader_image_load_store-shader-mem-barrier
See HSD ES # 1404612949
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Francisco Jerez <curroje...@riseup.net>
---
src/intel/compiler/brw_eu_emit.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 44abede16b..f8102e014e 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3287,7 +3287,9 @@ brw_memory_fence(struct brw_codegen *p,
struct brw_reg dst)
{
const struct gen_device_info *devinfo = p->devinfo;
- const bool commit_enable = devinfo->gen == 7 && !devinfo->is_haswell;
+ const bool commit_enable =
+ devinfo->gen >= 10 || /* HSD ES # 1404612949 */
+ (devinfo->gen == 7 && !devinfo->is_haswell);
struct brw_inst *insn;
brw_push_insn_state(p);
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