Module: Mesa Branch: master Commit: 4fdce205dd1f5ca42c6e45ff7b0b8c2f870638ba URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fdce205dd1f5ca42c6e45ff7b0b8c2f870638ba
Author: Grazvydas Ignotas <[email protected]> Date: Thu May 10 00:26:21 2018 +0300 radv: assorted typo fixes Trivial. Reviewed-by: Samuel Pitoiset <[email protected]> --- src/amd/vulkan/radv_cmd_buffer.c | 4 ++-- src/amd/vulkan/radv_descriptor_set.c | 2 +- src/amd/vulkan/radv_device.c | 6 +++--- src/amd/vulkan/radv_entrypoints_gen.py | 2 +- src/amd/vulkan/radv_image.c | 4 ++-- src/amd/vulkan/radv_nir_to_llvm.c | 4 ++-- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index baa28d408b..1ca687494a 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -238,7 +238,7 @@ static VkResult radv_create_cmd_buffer( cmd_buffer->queue_family_index = pool->queue_family_index; } else { - /* Init the pool_link so we can safefly call list_del when we destroy + /* Init the pool_link so we can safely call list_del when we destroy * the command buffer */ list_inithead(&cmd_buffer->pool_link); @@ -1156,7 +1156,7 @@ radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer, } /* - *with DCC some colors don't require CMASK elimiation before being + * With DCC some colors don't require CMASK elimination before being * used as a texture. This sets a predicate value to determine if the * cmask eliminate is required. */ diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index 4b08a1f0f8..9d783b8b6d 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++ b/src/amd/vulkan/radv_descriptor_set.c @@ -322,7 +322,7 @@ void radv_GetDescriptorSetLayoutSupport(VkDevice device, /* * Pipeline layouts. These have nothing to do with the pipeline. They are - * just muttiple descriptor set layouts pasted together + * just multiple descriptor set layouts pasted together. */ VkResult radv_CreatePipelineLayout( diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 9fe415c4e0..08795dd6b6 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -278,7 +278,7 @@ radv_physical_device_init(struct radv_physical_device *device, (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) | (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0); - /* The gpu id is already embeded in the uuid so we just pass "radv" + /* The gpu id is already embedded in the uuid so we just pass "radv" * when creating the cache. */ char buf[VK_UUID_SIZE * 2 + 1]; @@ -300,7 +300,7 @@ radv_physical_device_init(struct radv_physical_device *device, device->rad_info.family == CHIP_RAVEN; } - /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs + /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs * on SI. */ device->has_clear_state = device->rad_info.chip_class >= CIK; @@ -1466,7 +1466,7 @@ VkResult radv_CreateDevice( * evenly between CUs. The number is only a function of the number of CUs. * We can decrease the constant to decrease the scratch buffer size. * - * sctx->scratch_waves must be >= the maximum posible size of + * sctx->scratch_waves must be >= the maximum possible size of * 1 threadgroup, so that the hw doesn't hang from being unable * to start any. * diff --git a/src/amd/vulkan/radv_entrypoints_gen.py b/src/amd/vulkan/radv_entrypoints_gen.py index 892491e6c3..a201142986 100644 --- a/src/amd/vulkan/radv_entrypoints_gen.py +++ b/src/amd/vulkan/radv_entrypoints_gen.py @@ -116,7 +116,7 @@ struct string_map_entry { uint32_t num; }; -/* We use a big string constant to avoid lots of reloctions from the entry +/* We use a big string constant to avoid lots of relocations from the entry * point table to lots of little strings. The entries in the entry point table * store the index into this big string. */ diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index ad480901ee..5cdffe1627 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -414,7 +414,7 @@ static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type, else return V_008F1C_SQ_RSRC_IMG_2D_ARRAY; default: - unreachable("illegale image type"); + unreachable("illegal image type"); } } @@ -534,7 +534,7 @@ si_make_texture_descriptor(struct radv_device *device, if (device->physical_device->rad_info.chip_class >= GFX9) { unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle); - /* Depth is the the last accessible layer on Gfx9. + /* Depth is the last accessible layer on Gfx9. * The hw doesn't need to know the total number of layers. */ if (type == V_008F1C_SQ_RSRC_IMG_3D) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index a6b48e297d..e2d241e495 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -2522,7 +2522,7 @@ ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name) /* get current basic block */ current_block = LLVMGetInsertBlock(ctx->ac.builder); - /* chqeck if there's another block after this one */ + /* check if there's another block after this one */ next_block = LLVMGetNextBasicBlock(current_block); if (next_block) { /* insert the new block before the next block */ @@ -2647,7 +2647,7 @@ write_tess_factors(struct radv_shader_context *ctx) outer[i] = LLVMGetUndef(ctx->ac.i32); } - // LINES reverseal + // LINES reversal if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) { outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer); lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer, _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
