Module: Mesa
Branch: master
Commit: 4bdad9faddc82a4560603936ce5ade5707ecb254
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bdad9faddc82a4560603936ce5ade5707ecb254
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Date: Thu Jun 14 13:26:21 2018 +0200
radv: always set/load both depth and stencil clear values
I don't think that matter much to emit both values and that
makes the code a bit simpler.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
---
src/amd/vulkan/radv_cmd_buffer.c | 33 +++++----------------------------
1 file changed, 5 insertions(+), 28 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ad83bc6c6f..c2db11d041 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1210,29 +1210,17 @@ radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer,
{
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->clear_value_offset;
- unsigned reg_offset = 0, reg_count = 0;
assert(radv_image_has_htile(image));
- if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
- ++reg_count;
- } else {
- ++reg_offset;
- va += 4;
- }
- if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
- ++reg_count;
-
- radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
+ radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
radeon_emit(cmd_buffer->cs, va);
radeon_emit(cmd_buffer->cs, va >> 32);
- if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
- radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
- if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
- radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
+ radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
+ radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value);
@@ -1270,30 +1258,19 @@ static void
radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image)
{
- VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->clear_value_offset;
- unsigned reg_offset = 0, reg_count = 0;
if (!radv_image_has_htile(image))
return;
- if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
- ++reg_count;
- } else {
- ++reg_offset;
- va += 4;
- }
- if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
- ++reg_count;
-
radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
COPY_DATA_DST_SEL(COPY_DATA_REG) |
- (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
+ COPY_DATA_COUNT_SEL);
radeon_emit(cmd_buffer->cs, va);
radeon_emit(cmd_buffer->cs, va >> 32);
- radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 *
reg_offset) >> 2);
+ radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
radeon_emit(cmd_buffer->cs, 0);
radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
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