Module: Mesa Branch: master Commit: 7f95564a22d11ee3f54915ee02f9fa1f78c6adcf URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f95564a22d11ee3f54915ee02f9fa1f78c6adcf
Author: Karol Herbst <[email protected]> Date: Thu Apr 26 21:06:08 2018 +0200 nir: rename f2f16_undef to f2f16 we need rounding modes on other conversions involving floats and it is easier to rename f2f16_undef than renaming all the other ones. v2: rebased on master Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Rob Clark <[email protected]> Signed-off-by: Karol Herbst <[email protected]> --- src/amd/common/ac_nir_to_llvm.c | 2 +- src/compiler/nir/nir_opcodes.py | 4 ++-- src/compiler/nir/nir_opcodes_c.py | 8 ++++---- src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c | 6 +++--- src/intel/compiler/brw_fs_nir.cpp | 2 +- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 542b880e88..44361be0d3 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -889,7 +889,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, ""); break; case nir_op_f2f16_rtne: - case nir_op_f2f16_undef: + case nir_op_f2f16: case nir_op_f2f32: case nir_op_f2f64: src[0] = ac_to_float(&ctx->ac, src[0]); diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index b03c5da2ea..ed8e0ae9f3 100644 --- a/src/compiler/nir/nir_opcodes.py +++ b/src/compiler/nir/nir_opcodes.py @@ -181,9 +181,9 @@ for src_t in [tint, tuint, tfloat]: bit_sizes = [8, 16, 32, 64] for bit_size in bit_sizes: if bit_size == 16 and dst_t == tfloat and src_t == tfloat: - rnd_modes = ['rtne', 'rtz', 'undef'] + rnd_modes = ['_rtne', '_rtz', ''] for rnd_mode in rnd_modes: - unop_convert("{0}2{1}{2}_{3}".format(src_t[0], dst_t[0], + unop_convert("{0}2{1}{2}{3}".format(src_t[0], dst_t[0], bit_size, rnd_mode), dst_t + str(bit_size), src_t, "src0") else: diff --git a/src/compiler/nir/nir_opcodes_c.py b/src/compiler/nir/nir_opcodes_c.py index 4603cd3d74..8bfcda6d71 100644 --- a/src/compiler/nir/nir_opcodes_c.py +++ b/src/compiler/nir/nir_opcodes_c.py @@ -73,10 +73,10 @@ nir_type_conversion_op(nir_alu_type src, nir_alu_type dst, nir_rounding_mode rnd case ${dst_bits}: % if src_t == 'float' and dst_t == 'float' and dst_bits == 16: switch(rnd) { -% for rnd_t in ['rtne', 'rtz', 'undef']: - case nir_rounding_mode_${rnd_t}: - return ${'nir_op_{0}2{1}{2}_{3}'.format(src_t[0], dst_t[0], - dst_bits, rnd_t)}; +% for rnd_t in [('rtne', '_rtne'), ('rtz', '_rtz'), ('undef', '')]: + case nir_rounding_mode_${rnd_t[0]}: + return ${'nir_op_{0}2{1}{2}{3}'.format(src_t[0], dst_t[0], + dst_bits, rnd_t[1])}; % endfor default: unreachable("Invalid 16-bit nir rounding mode"); diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c index d8414903e7..6eb1e03e02 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c @@ -948,7 +948,7 @@ create_cov(struct ir3_context *ctx, struct ir3_instruction *src, case nir_op_f2f32: case nir_op_f2f16_rtne: case nir_op_f2f16_rtz: - case nir_op_f2f16_undef: + case nir_op_f2f16: case nir_op_f2i32: case nir_op_f2i16: case nir_op_f2i8: @@ -1020,7 +1020,7 @@ create_cov(struct ir3_context *ctx, struct ir3_instruction *src, case nir_op_f2f16_rtne: case nir_op_f2f16_rtz: - case nir_op_f2f16_undef: + case nir_op_f2f16: /* TODO how to handle rounding mode? */ case nir_op_i2f16: case nir_op_u2f16: @@ -1145,7 +1145,7 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) case nir_op_f2f32: case nir_op_f2f16_rtne: case nir_op_f2f16_rtz: - case nir_op_f2f16_undef: + case nir_op_f2f16: case nir_op_f2i32: case nir_op_f2i16: case nir_op_f2i8: diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index e983110027..9b11b5fbd0 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -787,7 +787,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7. */ - case nir_op_f2f16_undef: + case nir_op_f2f16: inst = bld.MOV(result, op[0]); inst->saturate = instr->dest.saturate; break; _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
