Module: Mesa Branch: fast-color-clear Commit: 460a4eb11f4c76b08439278486c6fb20bfb45956 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=460a4eb11f4c76b08439278486c6fb20bfb45956
Author: Plamena Manolova <[email protected]> Date: Tue Jan 15 22:39:31 2019 +0000 i965: Set clear color with MI_ATOMIC for GEN11 For GEN11 we need to set the clear color using two MI_ATOMIC commands. Signed-off-by: Plamena Manolova <[email protected]> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 52 +++++++++++++++++++++------ 1 file changed, 42 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 426782c5883..7ed1cde87fc 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -37,6 +37,7 @@ #include "brw_blorp.h" #include "brw_context.h" #include "brw_state.h" +#include "brw_defines.h" #include "main/enums.h" #include "main/fbobject.h" @@ -49,6 +50,7 @@ #include "util/format_srgb.h" #include "x86/common_x86_asm.h" +#include "intel/compiler/brw_eu_defines.h" #define FILE_DEBUG_FLAG DEBUG_MIPTREE @@ -3846,17 +3848,47 @@ intel_miptree_set_clear_color(struct brw_context *brw, if (memcmp(&mt->fast_clear_color, &clear_color, sizeof(clear_color)) != 0) { mt->fast_clear_color = clear_color; if (mt->aux_buf->clear_color_bo) { - /* We can't update the clear color while the hardware is still using - * the previous one for a resolve or sampling from it. Make sure that - * there are no pending commands at this point. - */ - brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL); - for (int i = 0; i < 4; i++) { - brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo, - mt->aux_buf->clear_color_offset + i * 4, - mt->fast_clear_color.u32[i]); + if (brw->screen->devinfo.gen == 11) { + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL); + BEGIN_BATCH(7); + OUT_BATCH(MI_ATOMIC | MI_ATOMIC_DATA_SIZE_QWORD | + MI_ATOMIC_INLINE_DATA | (BRW_AOP_MOV8 << 8) | (7 - 2)); + OUT_RELOC64(mt->aux_buf->clear_color_bo, RELOC_WRITE, + mt->aux_buf->clear_color_offset); + OUT_BATCH(mt->fast_clear_color.u32[0]); + OUT_BATCH(0x0); + OUT_BATCH(mt->fast_clear_color.u32[1]); + OUT_BATCH(0x0); + ADVANCE_BATCH(); + + BEGIN_BATCH(7); + OUT_BATCH(MI_ATOMIC | MI_ATOMIC_DATA_SIZE_QWORD | + MI_ATOMIC_INLINE_DATA | MI_ATOMIC_CS_STALL | + MI_ATOMIC_RETURN_DATA_CONTROL | (BRW_AOP_MOV8 << 8) | (7 - 2)); + OUT_RELOC64(mt->aux_buf->clear_color_bo, RELOC_WRITE, + mt->aux_buf->clear_color_offset + 8); + OUT_BATCH(mt->fast_clear_color.u32[2]); + OUT_BATCH(0x0); + OUT_BATCH(mt->fast_clear_color.u32[3]); + OUT_BATCH(0x0); + ADVANCE_BATCH(); + + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE); + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); + + } else { + /* We can't update the clear color while the hardware is still using + * the previous one for a resolve or sampling from it. Make sure that + * there are no pending commands at this point. + */ + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL); + for (int i = 0; i < 4; i++) { + brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo, + mt->aux_buf->clear_color_offset + i * 4, + mt->fast_clear_color.u32[i]); + } + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE); } - brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE); } brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE; return true; _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
