This massively reduces compiled size (4.9% of brw_wm_surface_state.o).
---
src/mesa/drivers/dri/i965/brw_defines.h | 34 +++++++++++-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 67 +++++++++++----------
2 files changed, 68 insertions(+), 33 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 5eb7892..84b51c8 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -28,7 +28,10 @@
* Authors:
* Keith Whitwell <ke...@tungstengraphics.com>
*/
-
+
+#define INTEL_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
+#define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK)
+#define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
#ifndef BRW_DEFINES_H
#define BRW_DEFINES_H
@@ -243,8 +246,11 @@
#define BRW_STENCILOP_DECR 6
#define BRW_STENCILOP_INVERT 7
+/* Surface state DW0 */
+#define BRW_SURFACE_MIPLAYOUT_SHIFT 10
#define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0
#define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1
+#define BRW_SURFACE_CUBEFACE_ENABLES 0x3f
#define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000
#define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001
@@ -403,10 +409,14 @@
#define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D
#define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E
#define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F
+#define BRW_SURFACE_FORMAT_SHIFT 18
+#define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
#define BRW_SURFACERETURNFORMAT_FLOAT32 0
#define BRW_SURFACERETURNFORMAT_S1 1
+#define BRW_SURFACE_TYPE_SHIFT 29
+#define BRW_SURFACE_TYPE_MASK INTEL_MASK(31, 29)
#define BRW_SURFACE_1D 0
#define BRW_SURFACE_2D 1
#define BRW_SURFACE_3D 2
@@ -414,6 +424,28 @@
#define BRW_SURFACE_BUFFER 4
#define BRW_SURFACE_NULL 7
+/* Surface state DW2 */
+#define BRW_SURFACE_HEIGHT_SHIFT 19
+#define BRW_SURFACE_HEIGHT_MASK INTEL_MASK(31, 19)
+#define BRW_SURFACE_WIDTH_SHIFT 6
+#define BRW_SURFACE_WIDTH_MASK INTEL_MASK(18, 6)
+#define BRW_SURFACE_LOD_SHIFT 2
+#define BRW_SURFACE_LOD_MASK INTEL_MASK(5, 2)
+
+/* Surface state DW3 */
+#define BRW_SURFACE_DEPTH_SHIFT 21
+#define BRW_SURFACE_DEPTH_MASK INTEL_MASK(31, 21)
+#define BRW_SURFACE_PITCH_SHIFT 3
+#define BRW_SURFACE_PITCH_MASK INTEL_MASK(19, 3)
+#define BRW_SURFACE_TILED (1 << 1)
+#define BRW_SURFACE_TILED_Y (1 << 0)
+
+/* Surface state DW5 */
+#define BRW_SURFACE_X_OFFSET_SHIFT 25
+#define BRW_SURFACE_X_OFFSET_MASK INTEL_MASK(31, 25)
+#define BRW_SURFACE_Y_OFFSET_SHIFT 20
+#define BRW_SURFACE_Y_OFFSET_MASK INTEL_MASK(23, 20)
+
#define BRW_TEXCOORDMODE_WRAP 0
#define BRW_TEXCOORDMODE_MIRROR 1
#define BRW_TEXCOORDMODE_CLAMP 2
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index f5c0694..fddab05 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -219,6 +219,19 @@ brw_set_surface_tiling(struct brw_surface_state *surf,
uint32_t tiling)
}
}
+static uint32_t
+brw_get_surface_tiling_bits(uint32_t tiling)
+{
+ switch (tiling) {
+ case I915_TILING_X:
+ return BRW_SURFACE_TILED;
+ case I915_TILING_Y:
+ return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
+ default:
+ return 0;
+ }
+}
+
static void
brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
{
@@ -228,46 +241,36 @@ brw_update_texture_surface( struct gl_context *ctx,
GLuint unit )
struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
- struct brw_surface_state *surf;
+ uint32_t *surf;
- surf = brw_state_batch(brw, sizeof(*surf), 32,
- &brw->wm.surf_offset[surf_index]);
- memset(surf, 0, sizeof(*surf));
+ surf = brw_state_batch(brw, 6 * 4, 32, &brw->wm.surf_offset[surf_index]);
- surf->ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
- surf->ss0.surface_type = translate_tex_target(tObj->Target);
- surf->ss0.surface_format = translate_tex_format(firstImage->TexFormat,
- firstImage->InternalFormat,
- sampler->DepthMode,
- sampler->sRGBDecode);
+ surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
+ BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
+ BRW_SURFACE_CUBEFACE_ENABLES |
+ (translate_tex_format(firstImage->TexFormat,
+ firstImage->InternalFormat,
+ sampler->DepthMode,
+ sampler->sRGBDecode) <<
+ BRW_SURFACE_FORMAT_SHIFT));
- /* This is ok for all textures with channel width 8bit or less:
- */
-/* surf->ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
- surf->ss1.base_addr = intelObj->mt->region->buffer->offset; /* reloc */
+ surf[1] = intelObj->mt->region->buffer->offset; /* reloc */
- surf->ss2.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
- surf->ss2.width = firstImage->Width - 1;
- surf->ss2.height = firstImage->Height - 1;
- brw_set_surface_tiling(surf, intelObj->mt->region->tiling);
- surf->ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
- surf->ss3.depth = firstImage->Depth - 1;
+ surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT
|
+ (firstImage->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
+ (firstImage->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
- surf->ss4.min_lod = 0;
-
- if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
- surf->ss0.cube_pos_x = 1;
- surf->ss0.cube_pos_y = 1;
- surf->ss0.cube_pos_z = 1;
- surf->ss0.cube_neg_x = 1;
- surf->ss0.cube_neg_y = 1;
- surf->ss0.cube_neg_z = 1;
- }
+ surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
+ (firstImage->Depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
+ ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
+ BRW_SURFACE_PITCH_SHIFT);
+
+ surf[4] = 0;
+ surf[5] = 0;
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->intel.batch.bo,
- brw->wm.surf_offset[surf_index] +
- offsetof(struct brw_surface_state, ss1),
+ brw->wm.surf_offset[surf_index] + 4,
intelObj->mt->region->buffer, 0,
I915_GEM_DOMAIN_SAMPLER, 0);
}
--
1.7.5.1
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
