[Mesa-dev] [PATCH] radeonsi: add loading doubles from lds and geom inputs

[Dave Airlie]

From: Dave Airlie <airl...@redhat.com>

This adds two cases of missing double handling to radeonsi,
one for loading doubles from LDS and one for fetch doubles
for geometry shader inputs.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/gallium/drivers/radeonsi/si_shader.c | 28 ++++++++++++++++++++++++----
 1 file changed, 24 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 14f12df..1baa2eb 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -594,6 +594,14 @@ static LLVMValueRef lds_load(struct lp_build_tgsi_context 
*bld_base,
                            lp_build_const_int32(gallivm, swizzle));
 
        value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
+       if (type == TGSI_TYPE_DOUBLE) {
+               LLVMValueRef value2;
+               dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
+                                      lp_build_const_int32(gallivm, swizzle + 
1));
+               value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, 
dw_addr);
+               return radeon_llvm_emit_fetch_double(bld_base, value, value2);
+       }
+
        return LLVMBuildBitCast(gallivm->builder, value,
                                tgsi2llvmtype(bld_base, type), "");
 }
@@ -733,6 +741,7 @@ static LLVMValueRef fetch_input_gs(
        unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
        unsigned semantic_index = 
info->input_semantic_index[reg->Register.Index];
        unsigned param;
+       LLVMValueRef value;
 
        if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
                return get_primitive_id(bld_base, swizzle);
@@ -774,11 +783,22 @@ static LLVMValueRef fetch_input_gs(
        args[7] = uint->zero; /* SLC */
        args[8] = uint->zero; /* TFE */
 
+       value = lp_build_intrinsic(gallivm->builder,
+                                  "llvm.SI.buffer.load.dword.i32.i32",
+                                  i32, args, 9,
+                                  LLVMReadOnlyAttribute | 
LLVMNoUnwindAttribute);
+       if (type == TGSI_TYPE_DOUBLE) {
+               LLVMValueRef value2;
+               args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 
1) * 256);
+               value2 = lp_build_intrinsic(gallivm->builder,
+                                           "llvm.SI.buffer.load.dword.i32.i32",
+                                           i32, args, 9,
+                                           LLVMReadOnlyAttribute | 
LLVMNoUnwindAttribute);
+               return radeon_llvm_emit_fetch_double(bld_base,
+                                                    value, value2);
+       }
        return LLVMBuildBitCast(gallivm->builder,
-                               lp_build_intrinsic(gallivm->builder,
-                                               
"llvm.SI.buffer.load.dword.i32.i32",
-                                               i32, args, 9,
-                                               LLVMReadOnlyAttribute | 
LLVMNoUnwindAttribute),
+                               value,
                                tgsi2llvmtype(bld_base, type), "");
 }
 
-- 
2.5.0

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