From: Krzysztof Sobiecki <sob...@gmail.com>

ALIGN_DIVUP is a driver specific(r600g) macro that duplicates DIV_ROUND_UP 
functionality.
Replacing it with DIV_ROUND_UP eliminates this problems.

Signed-off-by: Krzysztof A. Sobiecki <sob...@gmail.com>
---
 src/gallium/drivers/r600/evergreen_state.c | 2 +-
 src/gallium/drivers/r600/r600_pipe.h       | 1 -
 src/gallium/drivers/r600/r600_state.c      | 2 +-
 3 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 1aee7dd..9dfb849 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1956,7 +1956,7 @@ static void evergreen_emit_constant_buffers(struct 
r600_context *rctx,
 
                if (!gs_ring_buffer) {
                        radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + 
buffer_index * 4,
-                                                   
ALIGN_DIVUP(cb->buffer_size, 256), pkt_flags);
+                                                   
DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
                        radeon_set_context_reg_flag(cs, reg_alu_const_cache + 
buffer_index * 4, va >> 8,
                                                    pkt_flags);
                }
diff --git a/src/gallium/drivers/r600/r600_pipe.h 
b/src/gallium/drivers/r600/r600_pipe.h
index 31f2a72..0e4dd16 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -946,7 +946,6 @@ static inline uint32_t S_FIXED(float value, uint32_t 
frac_bits)
 {
        return value * (1 << frac_bits);
 }
-#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 
 /* 12.4 fixed-point */
 static inline unsigned r600_pack_float_12p4(float x)
diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index 43b8074..f60e304 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1768,7 +1768,7 @@ static void r600_emit_constant_buffers(struct 
r600_context *rctx,
 
                if (!gs_ring_buffer) {
                        radeon_set_context_reg(cs, reg_alu_constbuf_size + 
buffer_index * 4,
-                                              ALIGN_DIVUP(cb->buffer_size, 
256));
+                                              DIV_ROUND_UP(cb->buffer_size, 
256));
                        radeon_set_context_reg(cs, reg_alu_const_cache + 
buffer_index * 4, offset >> 8);
                }
 
-- 
2.7.0.rc0.173.g4a846af

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