Might be a good idea to update the comment above the second hunk. It's very
precise about which bits, and so now wrong.
- Chris
On Wed, Jan 27, 2016 at 12:44 PM, Ben Widawsky <benjamin.widaw...@intel.com>
wrote:
> Cc: Jordan Justen <jordan.l.jus...@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index aad512f..820c1d4 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -924,6 +924,8 @@ void
> fs_visitor::emit_barrier()
> {
> assert(devinfo->gen >= 7);
> + const uint32_t barrier_id_mask =
> + devinfo->gen >= 9 ? 0x8f000000u : 0x0f000000u;
>
> /* We are getting the barrier ID from the compute shader header */
> assert(stage == MESA_SHADER_COMPUTE);
> @@ -937,7 +939,7 @@ fs_visitor::emit_barrier()
>
> /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
> fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD));
> - pbld.AND(component(payload, 2), r0_2, brw_imm_ud(0x0f000000u));
> + pbld.AND(component(payload, 2), r0_2, brw_imm_ud(barrier_id_mask));
>
> /* Emit a gateway "barrier" message using the payload we set up,
> followed
> * by a wait instruction.
> --
> 2.7.0
>
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