Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Mon, 2016-01-25 at 15:18 -0800, Matt Turner wrote: > And mark nir_op_pack_uvec4_to_uint unreachable, since it's only produced > by lowering pack[SU]norm4x8 which the vec4 backend does not need. > --- > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > index 1b87e30..d3ac7ab 100644 > --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > @@ -1325,6 +1325,24 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) > case nir_op_pack_unorm_2x16: > unreachable("not reached: should be handled by > lower_packing_builtins"); > > + case nir_op_pack_uvec4_to_uint: > + unreachable("not reached"); > + > + case nir_op_pack_uvec2_to_uint: { > + dst_reg tmp1 = dst_reg(this, glsl_type::uint_type); > + tmp1.writemask = WRITEMASK_X; > + op[0].swizzle = BRW_SWIZZLE_YYYY; > + emit(SHL(tmp1, op[0], src_reg(brw_imm_ud(16u)))); > + > + dst_reg tmp2 = dst_reg(this, glsl_type::uint_type); > + tmp2.writemask = WRITEMASK_X; > + op[0].swizzle = BRW_SWIZZLE_XXXX; > + emit(AND(tmp2, op[0], src_reg(brw_imm_ud(0xffffu)))); > + > + emit(OR(dst, src_reg(tmp1), src_reg(tmp2))); > + break; > + } > + > case nir_op_unpack_half_2x16: > /* As NIR does not guarantee that we have a correct swizzle outside the > * boundaries of a vector, and the implementation of > emit_unpack_half_2x16
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