Because compute support is not enabled by default for these chipsets, NVF0_COMPUTE=1 needs to be used, along with GALLIUM_HUD to enable performance counters.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- .../drivers/nouveau/nvc0/nvc0_query_hw_sm.c | 755 ++++++++++++++++++--- .../drivers/nouveau/nvc0/nvc0_query_hw_sm.h | 2 + .../drivers/nouveau/nvc0/nve4_compute.xml.h | 4 + 3 files changed, 667 insertions(+), 94 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c index 68c8ff5..b584532 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c @@ -65,6 +65,7 @@ static const char *nve4_hw_sm_query_names[] = "local_load_transactions", "local_store", "local_store_transactions", + "not_predicated_off_thread_inst_executed", "prof_trigger_00", "prof_trigger_01", "prof_trigger_02", @@ -78,6 +79,7 @@ static const char *nve4_hw_sm_query_names[] = "shared_store", "shared_store_replay", "sm_cta_launched", + "thread_inst_executed", "threads_launched", "uncached_global_load_transaction", "warps_launched", @@ -169,6 +171,49 @@ static const uint64_t nve4_read_hw_sm_counters_code[] = 0x8000000000001de7ULL }; +static const uint64_t nvf0_read_hw_sm_counters_code[] = +{ + /* Same kernel as GK104:GK110 */ + 0x0880808080808080ULL, + 0x86400000109c0022ULL, + 0x86400000019c0032ULL, + 0x86400000021c0002ULL, + 0x86400000029c0006ULL, + 0x86400000031c000aULL, + 0x86400000039c000eULL, + 0x86400000041c0012ULL, + 0x08ac1080108c8080ULL, + 0x86400000049c0016ULL, + 0x86400000051c001aULL, + 0x86400000059c001eULL, + 0xdb201c007f9c201eULL, + 0x64c03c00001c002aULL, + 0xc00000020a1c3021ULL, + 0x64c03c00009c002eULL, + 0x0810a0808010b810ULL, + 0xc0000001041c3025ULL, + 0x180000000020003cULL, + 0xdb201c007f9c243eULL, + 0xc1c00000301c2021ULL, + 0xc1c00000081c2431ULL, + 0xc1c00000021c2435ULL, + 0xe0800000069c2026ULL, + 0x08b010b010b010a0ULL, + 0xe0800000061c2022ULL, + 0xe4c03c00051c0032ULL, + 0xe0840000041c282aULL, + 0xe4c03c00059c0036ULL, + 0xe08040007f9c2c2eULL, + 0xe0840000049c3032ULL, + 0xfe800000001c2800ULL, + 0x080000b81080b010ULL, + 0x64c03c00011c0002ULL, + 0xe08040007f9c3436ULL, + 0xfe80000020043010ULL, + 0xfc800000281c3000ULL, + 0x18000000001c003cULL, +}; + /* For simplicity, we will allocate as many group slots as we allocate counter * slots. This means that a single counter which wants to source from 2 groups * will have to be declared as using 2 counter slots. This shouldn't really be @@ -192,64 +237,539 @@ struct nvc0_hw_sm_query_cfg uint8_t norm[2]; /* normalization num,denom */ }; -#define _Q1A(n, f, m, g, s, nu, dn) [NVE4_HW_SM_QUERY_##n] = { { { f, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g, 0, s }, {}, {}, {} }, 1, { nu, dn } } -#define _Q1B(n, f, m, g, s, nu, dn) [NVE4_HW_SM_QUERY_##n] = { { { f, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g, 0, s }, {}, {}, {} }, 1, { nu, dn } } +#define _CA(f, m, g, s) { f, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g, 0, s } +#define _CB(f, m, g, s) { f, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g, 0, s } +#define _Q(n, c) [NVE4_HW_SM_QUERY_##n] = c + +/* ==== Compute capability 3.0 (GK104:GK110) ==== */ +static const struct nvc0_hw_sm_query_cfg +sm30_active_cycles = +{ + .ctr[0] = _CB(0x0001, B6, WARP, 0x00000000), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_active_warps = +{ + .ctr[0] = _CB(0x003f, B6, WARP, 0x31483104), + .num_counters = 1, + .norm = { 2, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_atom_cas_count = +{ + .ctr[0] = _CA(0x0001, B6, BRANCH, 0x000000004), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_atom_count = +{ + .ctr[0] = _CA(0x0001, B6, BRANCH, 0x00000000), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_branch = +{ + .ctr[0] = _CA(0x0001, B6, BRANCH, 0x0000000c), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_divergent_branch = +{ + .ctr[0] = _CA(0x0001, B6, BRANCH, 0x00000010), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_gld_request = +{ + .ctr[0] = _CA(0x0001, B6, LDST, 0x00000010), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_gld_mem_div_replay = +{ + .ctr[0] = _CB(0x0001, B6, REPLAY, 0x00000010), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_gst_transactions = +{ + .ctr[0] = _CB(0x0001, B6, MEM, 0x00000004), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_gst_mem_div_replay = +{ + .ctr[0] = _CB(0x0001, B6, REPLAY, 0x00000014), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_gred_count = +{ + .ctr[0] = _CA(0x0001, B6, BRANCH, 0x00000008), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_gst_request = +{ + .ctr[0] = _CA(0x0001, B6, LDST, 0x00000014), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_inst_executed = +{ + .ctr[0] = _CA(0x0003, B6, EXEC, 0x00000398), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_inst_issued1 = +{ + .ctr[0] = _CA(0x0001, B6, ISSUE, 0x00000004), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_inst_issued2 = +{ + .ctr[0] = _CA(0x0001, B6, ISSUE, 0x00000008), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_l1_gld_hit = +{ + .ctr[0] = _CB(0x0001, B6, L1, 0x00000010), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_l1_gld_miss = +{ + .ctr[0] = _CB(0x0001, B6, L1, 0x00000014), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_l1_gld_transactions = +{ + .ctr[0] = _CB(0x0001, B6, UNK0F, 0x00000000), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_l1_gst_transactions = +{ + .ctr[0] = _CB(0x0001, B6, UNK0F, 0x00000004), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_l1_local_ld_hit = +{ + .ctr[0] = _CB(0x0001, B6, L1, 0x00000000), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_l1_local_ld_miss = +{ + .ctr[0] = _CB(0x0001, B6, L1, 0x00000004), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_l1_local_st_hit = +{ + .ctr[0] = _CB(0x0001, B6, L1, 0x00000008), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_l1_local_st_miss = +{ + .ctr[0] = _CB(0x0001, B6, L1, 0x0000000c), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_l1_shared_ld_transactions = +{ + .ctr[0] = _CB(0x0001, B6, TRANSACTION, 0x00000008), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_l1_shared_st_transactions = +{ + .ctr[0] = _CB(0x0001, B6, TRANSACTION, 0x0000000c), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_local_ld = +{ + .ctr[0] = _CA(0x0001, B6, LDST, 0x00000008), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_local_ld_transactions = +{ + .ctr[0] = _CB(0x0001, B6, TRANSACTION, 0x00000000), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_local_st = +{ + .ctr[0] = _CA(0x0001, B6, LDST, 0x0000000c), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_local_st_transactions = +{ + .ctr[0] = _CB(0x0001, B6, TRANSACTION, 0x00000004), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_prof_trigger_0 = +{ + .ctr[0] = _CA(0x0001, B6, USER, 0x00000000), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_prof_trigger_1 = +{ + .ctr[0] = _CA(0x0001, B6, USER, 0x00000004), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_prof_trigger_2 = +{ + .ctr[0] = _CA(0x0001, B6, USER, 0x00000008), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_prof_trigger_3 = +{ + .ctr[0] = _CA(0x0001, B6, USER, 0x0000000c), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_prof_trigger_4 = +{ + .ctr[0] = _CA(0x0001, B6, USER, 0x00000010), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_prof_trigger_5 = +{ + .ctr[0] = _CA(0x0001, B6, USER, 0x00000014), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_prof_trigger_6 = +{ + .ctr[0] = _CA(0x0001, B6, USER, 0x00000018), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_prof_trigger_7 = +{ + .ctr[0] = _CA(0x0001, B6, USER, 0x0000001c), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_shared_ld = +{ + .ctr[0] = _CA(0x0001, B6, LDST, 0x00000000), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_shared_ld_replay = +{ + .ctr[0] = _CB(0x0001, B6, REPLAY, 0x00000008), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_shared_st = +{ + .ctr[0] = _CA(0x0001, B6, LDST, 0x00000004), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_shared_st_replay = +{ + .ctr[0] = _CB(0x0001, B6, REPLAY, 0x0000000c), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_sm_cta_launched = +{ + .ctr[0] = _CB(0x0001, B6, WARP, 0x0000001c), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_threads_launched = +{ + .ctr[0] = _CA(0x003f, B6, LAUNCH, 0x398a4188), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_uncached_gld_transactions = +{ + .ctr[0] = _CB(0x0001, B6, MEM, 0x00000000), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm30_warps_launched = +{ + .ctr[0] = _CA(0x0001, B6, LAUNCH, 0x00000004), + .num_counters = 1, + .norm = { 1, 1 }, +}; /* NOTES: * active_warps: bit 0 alternates btw 0 and 1 for odd nr of warps * inst_executed etc.: we only count a single warp scheduler */ -static const struct nvc0_hw_sm_query_cfg nve4_hw_sm_queries[] = -{ - _Q1B(ACTIVE_CYCLES, 0x0001, B6, WARP, 0x00000000, 1, 1), - _Q1B(ACTIVE_WARPS, 0x003f, B6, WARP, 0x31483104, 2, 1), - _Q1A(ATOM_CAS_COUNT, 0x0001, B6, BRANCH, 0x000000004, 1, 1), - _Q1A(ATOM_COUNT, 0x0001, B6, BRANCH, 0x00000000, 1, 1), - _Q1A(BRANCH, 0x0001, B6, BRANCH, 0x0000000c, 1, 1), - _Q1A(DIVERGENT_BRANCH, 0x0001, B6, BRANCH, 0x00000010, 1, 1), - _Q1A(GLD_REQUEST, 0x0001, B6, LDST, 0x00000010, 1, 1), - _Q1B(GLD_MEM_DIV_REPLAY, 0x0001, B6, REPLAY, 0x00000010, 1, 1), - _Q1B(GST_TRANSACTIONS, 0x0001, B6, MEM, 0x00000004, 1, 1), - _Q1B(GST_MEM_DIV_REPLAY, 0x0001, B6, REPLAY, 0x00000014, 1, 1), - _Q1A(GRED_COUNT, 0x0001, B6, BRANCH, 0x00000008, 1, 1), - _Q1A(GST_REQUEST, 0x0001, B6, LDST, 0x00000014, 1, 1), - _Q1A(INST_EXECUTED, 0x0003, B6, EXEC, 0x00000398, 1, 1), - _Q1A(INST_ISSUED1, 0x0001, B6, ISSUE, 0x00000004, 1, 1), - _Q1A(INST_ISSUED2, 0x0001, B6, ISSUE, 0x00000008, 1, 1), - _Q1B(L1_GLD_HIT, 0x0001, B6, L1, 0x00000010, 1, 1), - _Q1B(L1_GLD_MISS, 0x0001, B6, L1, 0x00000014, 1, 1), - _Q1B(L1_GLD_TRANSACTIONS, 0x0001, B6, UNK0F, 0x00000000, 1, 1), - _Q1B(L1_GST_TRANSACTIONS, 0x0001, B6, UNK0F, 0x00000004, 1, 1), - _Q1B(L1_LOCAL_LD_HIT, 0x0001, B6, L1, 0x00000000, 1, 1), - _Q1B(L1_LOCAL_LD_MISS, 0x0001, B6, L1, 0x00000004, 1, 1), - _Q1B(L1_LOCAL_ST_HIT, 0x0001, B6, L1, 0x00000008, 1, 1), - _Q1B(L1_LOCAL_ST_MISS, 0x0001, B6, L1, 0x0000000c, 1, 1), - _Q1B(L1_SHARED_LD_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x00000008, 1, 1), - _Q1B(L1_SHARED_ST_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x0000000c, 1, 1), - _Q1A(LOCAL_LD, 0x0001, B6, LDST, 0x00000008, 1, 1), - _Q1B(LOCAL_LD_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x00000000, 1, 1), - _Q1A(LOCAL_ST, 0x0001, B6, LDST, 0x0000000c, 1, 1), - _Q1B(LOCAL_ST_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x00000004, 1, 1), - _Q1A(PROF_TRIGGER_0, 0x0001, B6, USER, 0x00000000, 1, 1), - _Q1A(PROF_TRIGGER_1, 0x0001, B6, USER, 0x00000004, 1, 1), - _Q1A(PROF_TRIGGER_2, 0x0001, B6, USER, 0x00000008, 1, 1), - _Q1A(PROF_TRIGGER_3, 0x0001, B6, USER, 0x0000000c, 1, 1), - _Q1A(PROF_TRIGGER_4, 0x0001, B6, USER, 0x00000010, 1, 1), - _Q1A(PROF_TRIGGER_5, 0x0001, B6, USER, 0x00000014, 1, 1), - _Q1A(PROF_TRIGGER_6, 0x0001, B6, USER, 0x00000018, 1, 1), - _Q1A(PROF_TRIGGER_7, 0x0001, B6, USER, 0x0000001c, 1, 1), - _Q1A(SHARED_LD, 0x0001, B6, LDST, 0x00000000, 1, 1), - _Q1B(SHARED_LD_REPLAY, 0x0001, B6, REPLAY, 0x00000008, 1, 1), - _Q1A(SHARED_ST, 0x0001, B6, LDST, 0x00000004, 1, 1), - _Q1B(SHARED_ST_REPLAY, 0x0001, B6, REPLAY, 0x0000000c, 1, 1), - _Q1B(SM_CTA_LAUNCHED, 0x0001, B6, WARP, 0x0000001c, 1, 1), - _Q1A(THREADS_LAUNCHED, 0x003f, B6, LAUNCH, 0x398a4188, 1, 1), - _Q1B(UNCACHED_GLD_TRANSACTIONS, 0x0001, B6, MEM, 0x00000000, 1, 1), - _Q1A(WARPS_LAUNCHED, 0x0001, B6, LAUNCH, 0x00000004, 1, 1), -}; - -#undef _Q1A -#undef _Q1B +static const struct nvc0_hw_sm_query_cfg *sm30_hw_sm_queries[] = +{ + _Q(ACTIVE_CYCLES, &sm30_active_cycles), + _Q(ACTIVE_WARPS, &sm30_active_warps), + _Q(ATOM_CAS_COUNT, &sm30_atom_cas_count), + _Q(ATOM_COUNT, &sm30_atom_count), + _Q(BRANCH, &sm30_branch), + _Q(DIVERGENT_BRANCH, &sm30_divergent_branch), + _Q(GLD_REQUEST, &sm30_gld_request), + _Q(GLD_MEM_DIV_REPLAY, &sm30_gld_mem_div_replay), + _Q(GST_TRANSACTIONS, &sm30_gst_transactions), + _Q(GST_MEM_DIV_REPLAY, &sm30_gst_mem_div_replay), + _Q(GRED_COUNT, &sm30_gred_count), + _Q(GST_REQUEST, &sm30_gst_request), + _Q(INST_EXECUTED, &sm30_inst_executed), + _Q(INST_ISSUED1, &sm30_inst_issued1), + _Q(INST_ISSUED2, &sm30_inst_issued2), + _Q(L1_GLD_HIT, &sm30_l1_gld_hit), + _Q(L1_GLD_MISS, &sm30_l1_gld_miss), + _Q(L1_GLD_TRANSACTIONS, &sm30_l1_gld_transactions), + _Q(L1_GST_TRANSACTIONS, &sm30_l1_gst_transactions), + _Q(L1_LOCAL_LD_HIT, &sm30_l1_local_ld_hit), + _Q(L1_LOCAL_LD_MISS, &sm30_l1_local_ld_miss), + _Q(L1_LOCAL_ST_HIT, &sm30_l1_local_st_hit), + _Q(L1_LOCAL_ST_MISS, &sm30_l1_local_st_miss), + _Q(L1_SHARED_LD_TRANSACTIONS, &sm30_l1_shared_ld_transactions), + _Q(L1_SHARED_ST_TRANSACTIONS, &sm30_l1_shared_st_transactions), + _Q(LOCAL_LD, &sm30_local_ld), + _Q(LOCAL_LD_TRANSACTIONS, &sm30_local_ld_transactions), + _Q(LOCAL_ST, &sm30_local_st), + _Q(LOCAL_ST_TRANSACTIONS, &sm30_local_st_transactions), + _Q(NOT_PRED_OFF_INST_EXECUTED, NULL), + _Q(PROF_TRIGGER_0, &sm30_prof_trigger_0), + _Q(PROF_TRIGGER_1, &sm30_prof_trigger_1), + _Q(PROF_TRIGGER_2, &sm30_prof_trigger_2), + _Q(PROF_TRIGGER_3, &sm30_prof_trigger_3), + _Q(PROF_TRIGGER_4, &sm30_prof_trigger_4), + _Q(PROF_TRIGGER_5, &sm30_prof_trigger_5), + _Q(PROF_TRIGGER_6, &sm30_prof_trigger_6), + _Q(PROF_TRIGGER_7, &sm30_prof_trigger_7), + _Q(SHARED_LD, &sm30_shared_ld), + _Q(SHARED_LD_REPLAY, &sm30_shared_ld_replay), + _Q(SHARED_ST, &sm30_shared_st), + _Q(SHARED_ST_REPLAY, &sm30_shared_st_replay), + _Q(SM_CTA_LAUNCHED, &sm30_sm_cta_launched), + _Q(THREAD_INST_EXECUTED, NULL), + _Q(THREADS_LAUNCHED, &sm30_threads_launched), + _Q(UNCACHED_GLD_TRANSACTIONS, &sm30_uncached_gld_transactions), + _Q(WARPS_LAUNCHED, &sm30_warps_launched), +}; + +/* ==== Compute capability 3.5 (GK110/GK208) ==== */ +static const struct nvc0_hw_sm_query_cfg +sm35_atom_cas_count = +{ + .ctr[0] = _CA(0x0001, B6, UNK1A, 0x00000014), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm35_atom_count = +{ + .ctr[0] = _CA(0x0001, B6, UNK1A, 0x00000010), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm35_gred_count = +{ + .ctr[0] = _CA(0x0001, B6, UNK1A, 0x00000018), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm35_not_pred_off_inst_executed = +{ + .ctr[0] = _CA(0x003f, B6, UNK14, 0x29062080), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm35_shared_ld_replay = +{ + .ctr[0] = _CB(0xaaaa, LOGOP, UNK13, 0x00000018), + .ctr[1] = _CB(0x8888, LOGOP, REPLAY, 0x00000151), + .num_counters = 2, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm35_shared_st_replay = +{ + .ctr[0] = _CB(0xaaaa, LOGOP, UNK13, 0x00000018), + .ctr[1] = _CB(0x8888, LOGOP, REPLAY, 0x000001d1), + .num_counters = 2, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg +sm35_thread_inst_executed = +{ + .ctr[0] = _CA(0x003f, B6, UNK11, 0x29062080), + .num_counters = 1, + .norm = { 1, 1 }, +}; + +static const struct nvc0_hw_sm_query_cfg *sm35_hw_sm_queries[] = +{ + _Q(ACTIVE_CYCLES, &sm30_active_cycles), + _Q(ACTIVE_WARPS, &sm30_active_warps), + _Q(ATOM_CAS_COUNT, &sm35_atom_cas_count), + _Q(ATOM_COUNT, &sm35_atom_count), + _Q(BRANCH, NULL), + _Q(DIVERGENT_BRANCH, NULL), + _Q(GLD_REQUEST, &sm30_gld_request), + _Q(GLD_MEM_DIV_REPLAY, &sm30_gld_mem_div_replay), + _Q(GST_TRANSACTIONS, &sm30_gst_transactions), + _Q(GST_MEM_DIV_REPLAY, &sm30_gst_mem_div_replay), + _Q(GRED_COUNT, &sm35_gred_count), + _Q(GST_REQUEST, &sm30_gst_request), + _Q(INST_EXECUTED, &sm30_inst_executed), + _Q(INST_ISSUED1, &sm30_inst_issued1), + _Q(INST_ISSUED2, &sm30_inst_issued2), + _Q(L1_GLD_HIT, &sm30_l1_gld_hit), + _Q(L1_GLD_MISS, &sm30_l1_gld_miss), + _Q(L1_GLD_TRANSACTIONS, &sm30_l1_gld_transactions), + _Q(L1_GST_TRANSACTIONS, &sm30_l1_gst_transactions), + _Q(L1_LOCAL_LD_HIT, &sm30_l1_local_ld_hit), + _Q(L1_LOCAL_LD_MISS, &sm30_l1_local_ld_miss), + _Q(L1_LOCAL_ST_HIT, &sm30_l1_local_st_hit), + _Q(L1_LOCAL_ST_MISS, &sm30_l1_local_st_miss), + _Q(L1_SHARED_LD_TRANSACTIONS, &sm30_l1_shared_ld_transactions), + _Q(L1_SHARED_ST_TRANSACTIONS, &sm30_l1_shared_st_transactions), + _Q(LOCAL_LD, &sm30_local_ld), + _Q(LOCAL_LD_TRANSACTIONS, &sm30_local_ld_transactions), + _Q(LOCAL_ST, &sm30_local_st), + _Q(LOCAL_ST_TRANSACTIONS, &sm30_local_st_transactions), + _Q(NOT_PRED_OFF_INST_EXECUTED, &sm35_not_pred_off_inst_executed), + _Q(PROF_TRIGGER_0, &sm30_prof_trigger_0), + _Q(PROF_TRIGGER_1, &sm30_prof_trigger_1), + _Q(PROF_TRIGGER_2, &sm30_prof_trigger_2), + _Q(PROF_TRIGGER_3, &sm30_prof_trigger_3), + _Q(PROF_TRIGGER_4, &sm30_prof_trigger_4), + _Q(PROF_TRIGGER_5, &sm30_prof_trigger_5), + _Q(PROF_TRIGGER_6, &sm30_prof_trigger_6), + _Q(PROF_TRIGGER_7, &sm30_prof_trigger_7), + _Q(SHARED_LD, &sm30_shared_ld), + _Q(SHARED_LD_REPLAY, &sm35_shared_ld_replay), + _Q(SHARED_ST, &sm30_shared_st), + _Q(SHARED_ST_REPLAY, &sm35_shared_st_replay), + _Q(SM_CTA_LAUNCHED, &sm30_sm_cta_launched), + _Q(THREAD_INST_EXECUTED, &sm35_thread_inst_executed), + _Q(THREADS_LAUNCHED, &sm30_threads_launched), + _Q(UNCACHED_GLD_TRANSACTIONS, &sm30_uncached_gld_transactions), + _Q(WARPS_LAUNCHED, &sm30_warps_launched), +}; + +#undef _Q +#undef _CA +#undef _CB /* === PERFORMANCE MONITORING COUNTERS for NVC0:NVE4 === */ /* NOTES: @@ -753,11 +1273,28 @@ static const struct nvc0_hw_sm_query_cfg *sm21_hw_sm_queries[] = static inline const struct nvc0_hw_sm_query_cfg ** nvc0_hw_sm_get_queries(struct nvc0_screen *screen) { + const struct nvc0_hw_sm_query_cfg **queries = NULL; struct nouveau_device *dev = screen->base.device; - if (dev->chipset == 0xc0 || dev->chipset == 0xc8) - return sm20_hw_sm_queries; - return sm21_hw_sm_queries; + switch (dev->chipset & ~0xf) { + case 0xc0: + case 0xd0: + if (dev->chipset == 0xc0 || dev->chipset == 0xc8) + queries = sm20_hw_sm_queries; + else + queries = sm21_hw_sm_queries; + break; + case 0xe0: + queries = sm30_hw_sm_queries; + break; + case 0xf0: + case 0x100: + queries = sm35_hw_sm_queries; + break; + default: + break; + } + return queries; } static const struct nvc0_hw_sm_query_cfg * @@ -766,13 +1303,14 @@ nvc0_hw_sm_query_get_cfg(struct nvc0_context *nvc0, struct nvc0_hw_query *hq) struct nvc0_screen *screen = nvc0->screen; struct nvc0_query *q = &hq->base; - if (screen->base.class_3d >= NVE4_3D_CLASS) - return &nve4_hw_sm_queries[q->type - PIPE_QUERY_DRIVER_SPECIFIC]; - - if (q->type >= NVC0_HW_SM_QUERY(0) && q->type <= NVC0_HW_SM_QUERY_LAST) { + if ((q->type >= NVC0_HW_SM_QUERY(0) && q->type <= NVC0_HW_SM_QUERY_LAST) || + (q->type >= NVE4_HW_SM_QUERY(0) && q->type <= NVE4_HW_SM_QUERY_LAST)) { const struct nvc0_hw_sm_query_cfg **queries = nvc0_hw_sm_get_queries(screen); - return queries[q->type - NVC0_HW_SM_QUERY(0)]; + + if (q->type >= NVC0_HW_SM_QUERY(0) && q->type <= NVC0_HW_SM_QUERY_LAST) + return queries[q->type - NVC0_HW_SM_QUERY(0)]; + return queries[q->type - NVE4_HW_SM_QUERY(0)]; } debug_printf("invalid query type: %d\n", q->type); return NULL; @@ -929,6 +1467,36 @@ nvc0_hw_sm_begin_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq) return true; } +static inline struct nvc0_program * +nvc0_hw_sm_get_program(struct nvc0_screen *screen) +{ + struct nvc0_program *prog; + + prog = CALLOC_STRUCT(nvc0_program); + if (!prog) + return NULL; + + prog->type = PIPE_SHADER_COMPUTE; + prog->translated = true; + prog->parm_size = 12; + + if (screen->base.class_3d >= NVE4_3D_CLASS) { + if (screen->base.class_3d == NVE4_3D_CLASS) { + prog->code = (uint32_t *)nve4_read_hw_sm_counters_code; + prog->code_size = sizeof(nve4_read_hw_sm_counters_code); + } else { + prog->code = (uint32_t *)nvf0_read_hw_sm_counters_code; + prog->code_size = sizeof(nvf0_read_hw_sm_counters_code); + } + prog->num_gprs = 14; + } else { + prog->code = (uint32_t *)nvc0_read_hw_sm_counters_code; + prog->code_size = sizeof(nvc0_read_hw_sm_counters_code); + prog->num_gprs = 12; + } + return prog; +} + static void nvc0_hw_sm_end_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq) { @@ -944,22 +1512,8 @@ nvc0_hw_sm_end_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq) const uint grid[3] = { screen->mp_count, screen->gpc_count, 1 }; unsigned c, i; - if (unlikely(!screen->pm.prog)) { - struct nvc0_program *prog = CALLOC_STRUCT(nvc0_program); - prog->type = PIPE_SHADER_COMPUTE; - prog->translated = true; - prog->parm_size = 12; - if (is_nve4) { - prog->code = (uint32_t *)nve4_read_hw_sm_counters_code; - prog->code_size = sizeof(nve4_read_hw_sm_counters_code); - prog->num_gprs = 14; - } else { - prog->code = (uint32_t *)nvc0_read_hw_sm_counters_code; - prog->code_size = sizeof(nvc0_read_hw_sm_counters_code); - prog->num_gprs = 12; - } - screen->pm.prog = prog; - } + if (unlikely(!screen->pm.prog)) + screen->pm.prog = nvc0_hw_sm_get_program(screen); /* disable all counting */ PUSH_SPACE(push, 8); @@ -1096,6 +1650,8 @@ nvc0_hw_sm_get_query_result(struct nvc0_context *nvc0, struct nvc0_hw_query *hq, const struct nvc0_hw_sm_query_cfg *cfg; bool ret; + fprintf(stderr, "nvc0_hw_sm_get_query_result() called\n"); + cfg = nvc0_hw_sm_query_get_cfg(nvc0, hq); if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) @@ -1110,6 +1666,7 @@ nvc0_hw_sm_get_query_result(struct nvc0_context *nvc0, struct nvc0_hw_query *hq, value += count[p][c]; value = (value * cfg->norm[0]) / cfg->norm[1]; + fprintf(stderr, "-------> %d\n", value); *(uint64_t *)result = value; return true; } @@ -1202,12 +1759,14 @@ nvc0_hw_sm_create_query(struct nvc0_context *nvc0, unsigned type) } static int -nvc0_hw_sm_get_next_query_id(const struct nvc0_hw_sm_query_cfg **queries, +nvc0_hw_sm_get_next_query_id(struct nvc0_screen *screen, unsigned num_queries, unsigned id) { + const struct nvc0_hw_sm_query_cfg **queries; unsigned i, next = 0; - for (i = 0; i < NVC0_HW_SM_QUERY_COUNT; i++) { + queries = nvc0_hw_sm_get_queries(screen); + for (i = 0; i < num_queries; i++) { if (!queries[i]) { next++; } else @@ -1218,6 +1777,21 @@ nvc0_hw_sm_get_next_query_id(const struct nvc0_hw_sm_query_cfg **queries, return id + next; } +static int +nvc0_hw_sm_count_queries(struct nvc0_screen *screen, unsigned num_queries) +{ + const struct nvc0_hw_sm_query_cfg **queries; + int count = 0; + unsigned i; + + queries = nvc0_hw_sm_get_queries(screen); + for (i = 0; i < num_queries; i++) { + if (queries[i]) + count++; + } + return count; +} + int nvc0_hw_sm_get_driver_query_info(struct nvc0_screen *screen, unsigned id, struct pipe_driver_query_info *info) @@ -1226,18 +1800,11 @@ nvc0_hw_sm_get_driver_query_info(struct nvc0_screen *screen, unsigned id, if (screen->base.drm->version >= 0x01000101) { if (screen->compute) { - if (screen->base.class_3d == NVE4_3D_CLASS) { - count += NVE4_HW_SM_QUERY_COUNT; + if (screen->base.class_3d >= NVE4_3D_CLASS) { + count += nvc0_hw_sm_count_queries(screen, NVE4_HW_SM_QUERY_COUNT); } else if (screen->base.class_3d < NVE4_3D_CLASS) { - const struct nvc0_hw_sm_query_cfg **queries = - nvc0_hw_sm_get_queries(screen); - unsigned i; - - for (i = 0; i < NVC0_HW_SM_QUERY_COUNT; i++) { - if (queries[i]) - count++; - } + count += nvc0_hw_sm_count_queries(screen, NVC0_HW_SM_QUERY_COUNT); } } } @@ -1247,17 +1814,17 @@ nvc0_hw_sm_get_driver_query_info(struct nvc0_screen *screen, unsigned id, if (id < count) { if (screen->compute) { - if (screen->base.class_3d == NVE4_3D_CLASS) { + if (screen->base.class_3d >= NVE4_3D_CLASS) { + id = nvc0_hw_sm_get_next_query_id(screen, + NVE4_HW_SM_QUERY_COUNT, id); info->name = nve4_hw_sm_query_names[id]; info->query_type = NVE4_HW_SM_QUERY(id); info->group_id = NVC0_HW_SM_QUERY_GROUP; return 1; } else if (screen->base.class_3d < NVE4_3D_CLASS) { - const struct nvc0_hw_sm_query_cfg **queries = - nvc0_hw_sm_get_queries(screen); - - id = nvc0_hw_sm_get_next_query_id(queries, id); + id = nvc0_hw_sm_get_next_query_id(screen, + NVC0_HW_SM_QUERY_COUNT, id); info->name = nvc0_hw_sm_query_names[id]; info->query_type = NVC0_HW_SM_QUERY(id); info->group_id = NVC0_HW_SM_QUERY_GROUP; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.h b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.h index 94d55a0..5e2fef5 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.h +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.h @@ -50,6 +50,7 @@ enum nve4_hw_sm_queries NVE4_HW_SM_QUERY_LOCAL_LD_TRANSACTIONS, NVE4_HW_SM_QUERY_LOCAL_ST, NVE4_HW_SM_QUERY_LOCAL_ST_TRANSACTIONS, + NVE4_HW_SM_QUERY_NOT_PRED_OFF_INST_EXECUTED, NVE4_HW_SM_QUERY_PROF_TRIGGER_0, NVE4_HW_SM_QUERY_PROF_TRIGGER_1, NVE4_HW_SM_QUERY_PROF_TRIGGER_2, @@ -63,6 +64,7 @@ enum nve4_hw_sm_queries NVE4_HW_SM_QUERY_SHARED_ST, NVE4_HW_SM_QUERY_SHARED_ST_REPLAY, NVE4_HW_SM_QUERY_SM_CTA_LAUNCHED, + NVE4_HW_SM_QUERY_THREAD_INST_EXECUTED, NVE4_HW_SM_QUERY_THREADS_LAUNCHED, NVE4_HW_SM_QUERY_UNCACHED_GLD_TRANSACTIONS, NVE4_HW_SM_QUERY_WARPS_LAUNCHED, diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.xml.h b/src/gallium/drivers/nouveau/nvc0/nve4_compute.xml.h index 3fff112..3cc1d57 100644 --- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.xml.h +++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.xml.h @@ -294,6 +294,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVE4_COMPUTE_MP_PM_A_SIGSEL_LAUNCH 0x00000003 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_EXEC 0x00000004 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_ISSUE 0x00000005 +#define NVE4_COMPUTE_MP_PM_A_SIGSEL_UNK11 0x00000011 +#define NVE4_COMPUTE_MP_PM_A_SIGSEL_UNK14 0x00000014 +#define NVE4_COMPUTE_MP_PM_A_SIGSEL_UNK1A 0x0000001a #define NVE4_COMPUTE_MP_PM_A_SIGSEL_LDST 0x0000001b #define NVE4_COMPUTE_MP_PM_A_SIGSEL_BRANCH 0x0000001c @@ -307,6 +310,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVE4_COMPUTE_MP_PM_B_SIGSEL_UNK0F 0x0000000f #define NVE4_COMPUTE_MP_PM_B_SIGSEL_L1 0x00000010 #define NVE4_COMPUTE_MP_PM_B_SIGSEL_MEM 0x00000011 +#define NVE4_COMPUTE_MP_PM_B_SIGSEL_UNK13 0x00000013 #define NVE4_COMPUTE_MP_PM_SRCSEL(i0) (0x0000339c + 0x4*(i0)) #define NVE4_COMPUTE_MP_PM_SRCSEL__ESIZE 0x00000004 -- 2.6.4 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev