From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/r300/r300_texture.c | 22 ++++-----
src/gallium/drivers/radeon/r600_texture.c | 52 ++++++++++----------
src/gallium/drivers/radeon/radeon_winsys.h | 43 +++++++----------
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 59 +++++++++--------------
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 68 ++++++++++-----------------
5 files changed, 104 insertions(+), 140 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_texture.c
b/src/gallium/drivers/r300/r300_texture.c
index e90e741..3631cd1 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -1005,6 +1005,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
{
struct radeon_winsys *rws = rscreen->rws;
struct r300_resource *tex = NULL;
+ struct radeon_bo_tiling_info tiling = {};
tex = CALLOC_STRUCT(r300_resource);
if (!tex) {
@@ -1059,10 +1060,10 @@ r300_texture_create_object(struct r300_screen *rscreen,
util_format_is_depth_or_stencil(base->format) ? "depth" :
"color");
}
- rws->buffer_set_tiling(tex->buf, NULL,
- tex->tex.microtile, tex->tex.macrotile[0],
- 0, 0, 0, 0, 0, 0, 0,
- tex->tex.stride_in_bytes[0], false);
+ tiling.microtile = tex->tex.microtile;
+ tiling.macrotile = tex->tex.macrotile[0];
+ tiling.stride = tex->tex.stride_in_bytes[0];
+ rws->buffer_set_tiling(tex->buf, NULL, &tiling);
return tex;
@@ -1102,8 +1103,8 @@ struct pipe_resource *r300_texture_from_handle(struct
pipe_screen *screen,
struct r300_screen *rscreen = r300_screen(screen);
struct radeon_winsys *rws = rscreen->rws;
struct pb_buffer *buffer;
- enum radeon_bo_layout microtile, macrotile;
unsigned stride;
+ struct radeon_bo_tiling_info tiling = {};
/* Support only 2D textures without mipmaps */
if ((base->target != PIPE_TEXTURE_2D &&
@@ -1117,25 +1118,24 @@ struct pipe_resource *r300_texture_from_handle(struct
pipe_screen *screen,
if (!buffer)
return NULL;
- rws->buffer_get_tiling(buffer, µtile, ¯otile, NULL, NULL, NULL,
- NULL, NULL, NULL);
+ rws->buffer_get_tiling(buffer, &tiling);
/* Enforce a microtiled zbuffer. */
if (util_format_is_depth_or_stencil(base->format) &&
- microtile == RADEON_LAYOUT_LINEAR) {
+ tiling.microtile == RADEON_LAYOUT_LINEAR) {
switch (util_format_get_blocksize(base->format)) {
case 4:
- microtile = RADEON_LAYOUT_TILED;
+ tiling.microtile = RADEON_LAYOUT_TILED;
break;
case 2:
- microtile = RADEON_LAYOUT_SQUARETILED;
+ tiling.microtile = RADEON_LAYOUT_SQUARETILED;
break;
}
}
return (struct pipe_resource*)
- r300_texture_create_object(rscreen, base, microtile, macrotile,
+ r300_texture_create_object(rscreen, base, tiling.microtile,
tiling.macrotile,
stride, buffer);
}
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index af206e4..73e1101 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -236,20 +236,23 @@ static boolean r600_texture_get_handle(struct
pipe_screen* screen,
struct r600_resource *resource = &rtex->resource;
struct radeon_surf *surface = &rtex->surface;
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
-
- rscreen->ws->buffer_set_tiling(resource->buf,
- NULL,
- surface->level[0].mode >=
RADEON_SURF_MODE_1D ?
- RADEON_LAYOUT_TILED :
RADEON_LAYOUT_LINEAR,
- surface->level[0].mode >=
RADEON_SURF_MODE_2D ?
- RADEON_LAYOUT_TILED :
RADEON_LAYOUT_LINEAR,
- surface->pipe_config,
- surface->bankw, surface->bankh,
- surface->tile_split,
- surface->stencil_tile_split,
- surface->mtilea, surface->num_banks,
- surface->level[0].pitch_bytes,
- (surface->flags & RADEON_SURF_SCANOUT)
!= 0);
+ struct radeon_bo_tiling_info tiling = {};
+
+ tiling.microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
+ RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+ tiling.macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
+ RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+ tiling.pipe_config = surface->pipe_config;
+ tiling.bankw = surface->bankw;
+ tiling.bankh = surface->bankh;
+ tiling.tile_split = surface->tile_split;
+ tiling.stencil_tile_split = surface->stencil_tile_split;
+ tiling.mtilea = surface->mtilea;
+ tiling.num_banks = surface->num_banks;
+ tiling.stride = surface->level[0].pitch_bytes;
+ tiling.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
+
+ rscreen->ws->buffer_set_tiling(resource->buf, NULL, &tiling);
return rscreen->ws->buffer_get_handle(resource->buf,
surface->level[0].pitch_bytes,
whandle);
@@ -883,10 +886,9 @@ static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen *screen
struct pb_buffer *buf = NULL;
unsigned stride = 0;
unsigned array_mode;
- enum radeon_bo_layout micro, macro;
struct radeon_surf surface;
- bool scanout;
int r;
+ struct radeon_bo_tiling_info tiling = {};
/* Support only 2D textures without mipmaps */
if ((templ->target != PIPE_TEXTURE_2D && templ->target !=
PIPE_TEXTURE_RECT) ||
@@ -897,15 +899,17 @@ static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen *screen
if (!buf)
return NULL;
- rscreen->ws->buffer_get_tiling(buf, µ, ¯o,
- &surface.bankw, &surface.bankh,
- &surface.tile_split,
- &surface.stencil_tile_split,
- &surface.mtilea, &scanout);
+ rscreen->ws->buffer_get_tiling(buf, &tiling);
+
+ surface.bankw = tiling.bankw;
+ surface.bankh = tiling.bankh;
+ surface.tile_split = tiling.tile_split;
+ surface.stencil_tile_split = tiling.stencil_tile_split;
+ surface.mtilea = tiling.mtilea;
- if (macro == RADEON_LAYOUT_TILED)
+ if (tiling.macrotile == RADEON_LAYOUT_TILED)
array_mode = RADEON_SURF_MODE_2D;
- else if (micro == RADEON_LAYOUT_TILED)
+ else if (tiling.microtile == RADEON_LAYOUT_TILED)
array_mode = RADEON_SURF_MODE_1D;
else
array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
@@ -915,7 +919,7 @@ static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen *screen
return NULL;
}
- if (scanout)
+ if (tiling.scanout)
surface.flags |= RADEON_SURF_SCANOUT;
return (struct pipe_resource *)r600_texture_create_object(screen, templ,
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index 1160d23..c3539c1 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -276,6 +276,20 @@ struct radeon_info {
uint32_t cik_macrotile_mode_array[16];
};
+struct radeon_bo_tiling_info {
+ enum radeon_bo_layout microtile;
+ enum radeon_bo_layout macrotile;
+ unsigned pipe_config;
+ unsigned bankw;
+ unsigned bankh;
+ unsigned tile_split;
+ unsigned stencil_tile_split;
+ unsigned mtilea;
+ unsigned num_banks;
+ unsigned stride;
+ bool scanout;
+};
+
enum radeon_feature_id {
RADEON_FID_R300_HYPERZ_ACCESS, /* ZMask + HiZ */
RADEON_FID_R300_CMASK_ACCESS,
@@ -457,42 +471,21 @@ struct radeon_winsys {
* Return tiling flags describing a memory layout of a buffer object.
*
* \param buf A winsys buffer object to get the flags from.
- * \param macrotile A pointer to the return value of the microtile flag.
- * \param microtile A pointer to the return value of the macrotile flag.
- *
- * \note microtile and macrotile are not bitmasks!
+ * \param tiling Tiling info for display code and DRI sharing.
*/
void (*buffer_get_tiling)(struct pb_buffer *buf,
- enum radeon_bo_layout *microtile,
- enum radeon_bo_layout *macrotile,
- unsigned *bankw, unsigned *bankh,
- unsigned *tile_split,
- unsigned *stencil_tile_split,
- unsigned *mtilea,
- bool *scanout);
+ struct radeon_bo_tiling_info *tiling);
/**
* Set tiling flags describing a memory layout of a buffer object.
*
* \param buf A winsys buffer object to set the flags for.
* \param cs A command stream to flush if the buffer is referenced
by it.
- * \param macrotile A macrotile flag.
- * \param microtile A microtile flag.
- * \param stride A stride of the buffer in bytes, for texturing.
- *
- * \note microtile and macrotile are not bitmasks!
+ * \param tiling Tiling info for display code and DRI sharing.
*/
void (*buffer_set_tiling)(struct pb_buffer *buf,
struct radeon_winsys_cs *rcs,
- enum radeon_bo_layout microtile,
- enum radeon_bo_layout macrotile,
- unsigned pipe_config,
- unsigned bankw, unsigned bankh,
- unsigned tile_split,
- unsigned stencil_tile_split,
- unsigned mtilea, unsigned num_banks,
- unsigned stride,
- bool scanout);
+ struct radeon_bo_tiling_info *tiling);
/**
* Get a winsys buffer from a winsys handle. The internal structure
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 59a801b..469b702 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -391,13 +391,7 @@ static unsigned eg_tile_split_rev(unsigned eg_tile_split)
}
static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
- enum radeon_bo_layout *microtiled,
- enum radeon_bo_layout *macrotiled,
- unsigned *bankw, unsigned *bankh,
- unsigned *tile_split,
- unsigned *stencil_tile_split,
- unsigned *mtilea,
- bool *scanout)
+ struct radeon_bo_tiling_info *tiling)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
struct amdgpu_bo_info info = {0};
@@ -410,56 +404,45 @@ static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
tiling_flags = info.metadata.tiling_info;
- *microtiled = RADEON_LAYOUT_LINEAR;
- *macrotiled = RADEON_LAYOUT_LINEAR;
+ tiling->microtile = RADEON_LAYOUT_LINEAR;
+ tiling->macrotile = RADEON_LAYOUT_LINEAR;
if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */
- *macrotiled = RADEON_LAYOUT_TILED;
+ tiling->macrotile = RADEON_LAYOUT_TILED;
else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /*
1D_TILED_THIN1 */
- *microtiled = RADEON_LAYOUT_TILED;
+ tiling->microtile = RADEON_LAYOUT_TILED;
- if (bankw && tile_split && mtilea && tile_split) {
- *bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
- *bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
- *tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
- *mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
- }
- if (scanout)
- *scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /*
DISPLAY */
+ tiling->bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
+ tiling->bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
+ tiling->tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags,
TILE_SPLIT));
+ tiling->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
+ tiling->scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /*
DISPLAY */
}
static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
struct radeon_winsys_cs *rcs,
- enum radeon_bo_layout microtiled,
- enum radeon_bo_layout macrotiled,
- unsigned pipe_config,
- unsigned bankw, unsigned bankh,
- unsigned tile_split,
- unsigned stencil_tile_split,
- unsigned mtilea, unsigned num_banks,
- uint32_t pitch,
- bool scanout)
+ struct radeon_bo_tiling_info *tiling)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
struct amdgpu_bo_metadata metadata = {0};
uint32_t tiling_flags = 0;
- if (macrotiled == RADEON_LAYOUT_TILED)
+ if (tiling->macrotile == RADEON_LAYOUT_TILED)
tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
- else if (microtiled == RADEON_LAYOUT_TILED)
+ else if (tiling->microtile == RADEON_LAYOUT_TILED)
tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
else
tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
- tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, pipe_config);
- tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(bankw));
- tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(bankh));
- if (tile_split)
- tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT,
eg_tile_split_rev(tile_split));
- tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(mtilea));
- tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(num_banks)-1);
+ tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, tiling->pipe_config);
+ tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(tiling->bankw));
+ tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT,
util_logbase2(tiling->bankh));
+ if (tiling->tile_split)
+ tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT,
eg_tile_split_rev(tiling->tile_split));
+ tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
util_logbase2(tiling->mtilea));
+ tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS,
util_logbase2(tiling->num_banks)-1);
- if (scanout)
+ if (tiling->scanout)
tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /*
DISPLAY_MICRO_TILING */
else
tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /*
THIN_MICRO_TILING */
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 7e9ed0c..2ffa4e7 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -637,13 +637,7 @@ static unsigned eg_tile_split_rev(unsigned eg_tile_split)
}
static void radeon_bo_get_tiling(struct pb_buffer *_buf,
- enum radeon_bo_layout *microtiled,
- enum radeon_bo_layout *macrotiled,
- unsigned *bankw, unsigned *bankh,
- unsigned *tile_split,
- unsigned *stencil_tile_split,
- unsigned *mtilea,
- bool *scanout)
+ struct radeon_bo_tiling_info *tiling)
{
struct radeon_bo *bo = radeon_bo(_buf);
struct drm_radeon_gem_set_tiling args;
@@ -657,38 +651,28 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf,
&args,
sizeof(args));
- *microtiled = RADEON_LAYOUT_LINEAR;
- *macrotiled = RADEON_LAYOUT_LINEAR;
+ tiling->microtile = RADEON_LAYOUT_LINEAR;
+ tiling->macrotile = RADEON_LAYOUT_LINEAR;
if (args.tiling_flags & RADEON_TILING_MICRO)
- *microtiled = RADEON_LAYOUT_TILED;
+ tiling->microtile = RADEON_LAYOUT_TILED;
else if (args.tiling_flags & RADEON_TILING_MICRO_SQUARE)
- *microtiled = RADEON_LAYOUT_SQUARETILED;
+ tiling->microtile = RADEON_LAYOUT_SQUARETILED;
if (args.tiling_flags & RADEON_TILING_MACRO)
- *macrotiled = RADEON_LAYOUT_TILED;
- if (bankw && tile_split && stencil_tile_split && mtilea && tile_split) {
- *bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) &
RADEON_TILING_EG_BANKW_MASK;
- *bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) &
RADEON_TILING_EG_BANKH_MASK;
- *tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT)
& RADEON_TILING_EG_TILE_SPLIT_MASK;
- *stencil_tile_split = (args.tiling_flags >>
RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) &
RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
- *mtilea = (args.tiling_flags >>
RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) &
RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
- *tile_split = eg_tile_split(*tile_split);
- }
- if (scanout)
- *scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags &
RADEON_TILING_R600_NO_SCANOUT);
+ tiling->macrotile = RADEON_LAYOUT_TILED;
+
+ tiling->bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) &
RADEON_TILING_EG_BANKW_MASK;
+ tiling->bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) &
RADEON_TILING_EG_BANKH_MASK;
+ tiling->tile_split = (args.tiling_flags >>
RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
+ tiling->stencil_tile_split = (args.tiling_flags >>
RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) &
RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
+ tiling->mtilea = (args.tiling_flags >>
RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) &
RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
+ tiling->tile_split = eg_tile_split(tiling->tile_split);
+ tiling->scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags &
RADEON_TILING_R600_NO_SCANOUT);
}
static void radeon_bo_set_tiling(struct pb_buffer *_buf,
struct radeon_winsys_cs *rcs,
- enum radeon_bo_layout microtiled,
- enum radeon_bo_layout macrotiled,
- unsigned pipe_config,
- unsigned bankw, unsigned bankh,
- unsigned tile_split,
- unsigned stencil_tile_split,
- unsigned mtilea, unsigned num_banks,
- uint32_t pitch,
- bool scanout)
+ struct radeon_bo_tiling_info *tiling)
{
struct radeon_bo *bo = radeon_bo(_buf);
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
@@ -704,34 +688,34 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf,
os_wait_until_zero(&bo->num_active_ioctls, PIPE_TIMEOUT_INFINITE);
- if (microtiled == RADEON_LAYOUT_TILED)
+ if (tiling->microtile == RADEON_LAYOUT_TILED)
args.tiling_flags |= RADEON_TILING_MICRO;
- else if (microtiled == RADEON_LAYOUT_SQUARETILED)
+ else if (tiling->microtile == RADEON_LAYOUT_SQUARETILED)
args.tiling_flags |= RADEON_TILING_MICRO_SQUARE;
- if (macrotiled == RADEON_LAYOUT_TILED)
+ if (tiling->macrotile == RADEON_LAYOUT_TILED)
args.tiling_flags |= RADEON_TILING_MACRO;
- args.tiling_flags |= (bankw & RADEON_TILING_EG_BANKW_MASK) <<
+ args.tiling_flags |= (tiling->bankw & RADEON_TILING_EG_BANKW_MASK) <<
RADEON_TILING_EG_BANKW_SHIFT;
- args.tiling_flags |= (bankh & RADEON_TILING_EG_BANKH_MASK) <<
+ args.tiling_flags |= (tiling->bankh & RADEON_TILING_EG_BANKH_MASK) <<
RADEON_TILING_EG_BANKH_SHIFT;
- if (tile_split) {
- args.tiling_flags |= (eg_tile_split_rev(tile_split) &
+ if (tiling->tile_split) {
+ args.tiling_flags |= (eg_tile_split_rev(tiling->tile_split) &
RADEON_TILING_EG_TILE_SPLIT_MASK) <<
RADEON_TILING_EG_TILE_SPLIT_SHIFT;
}
- args.tiling_flags |= (stencil_tile_split &
+ args.tiling_flags |= (tiling->stencil_tile_split &
RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK) <<
RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
- args.tiling_flags |= (mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
+ args.tiling_flags |= (tiling->mtilea &
RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
- if (bo->rws->gen >= DRV_SI && !scanout)
+ if (bo->rws->gen >= DRV_SI && !tiling->scanout)
args.tiling_flags |= RADEON_TILING_R600_NO_SCANOUT;
args.handle = bo->handle;
- args.pitch = pitch;
+ args.pitch = tiling->stride;
drmCommandWriteRead(bo->rws->fd,
DRM_RADEON_GEM_SET_TILING,
--
2.5.0
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